US2019384869A1PendingUtilityA1

Integrated system of pdn implementation and digital co-synthesis

Assignee: CHAOYANG SEMICONDUCTOR JIANGYIN TECH CO LTDPriority: Jun 5, 2015Filed: Aug 26, 2019Published: Dec 19, 2019
Est. expiryJun 5, 2035(~8.9 yrs left)· nominal 20-yr term from priority
G06F 30/33G06F 30/367G06F 2119/06G06F 30/39G06F 30/327G06F 17/5068G06F 17/5022G06F 2217/78G06F 17/5036G06F 17/505G06F 30/3308
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Claims

Abstract

Design of a power delivery network (PDN) is integrated with a digital logic design flow.

Claims

exact text as granted — not AI-modified
1 . A method useful in integrated circuit design, comprising:
 receiving, by a computer, design parameters for a power delivery network (PDN) to be instantiated in an integrated circuit chip (IC);   receiving, by the computer, a model of logic circuitry for an integrated circuit;   simulating operation of a plurality of configurations of the PDN for the model of logic circuitry over a specified range of minimum voltages to indicate at least a best-for-area PDN configuration or a best-for-power PDN configuration of the plurality of configurations of the PDN;   generating, using the computer, a netlist of PDN components and interconnects for a selected PDN configuration, the selected PDN configuration being the best-for-area PDN configuration or the best-for-power PDN configuration;   instantiating the generated netlist into RTL models of a combined digital circuit design for the logic circuitry and selected PDN configuration; and   synthesizing the combined digital circuit design.   
     
     
         2 .- 4 . (canceled) 
     
     
         5 . The method of  claim 1 , wherein the parameters for the PDN comprise voltage regulator (VR) error, VR efficiency, and VR area. 
     
     
         6 . The method of  claim 5 , wherein the parameters for the PDN further comprise bump properties and on-die metal capacitor capacitance and area. 
     
     
         7 . The method of  claim 1 , wherein the model of logic circuitry comprises a model of area and current for the logic circuitry. 
     
     
         8 . The method of  claim 1 , wherein the netlist representation includes information regarding a number of bumps for the PDN. 
     
     
         9 . The method of  claim 1 , wherein the parameters for the PDN comprise automatic transient control (ATC) circuit area. 
     
     
         10 . The method of  claim 9 , wherein the netlist includes information regarding a number of embedded voltage regulators and a number of ATC circuits.

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