Performance By Retaining High Locality Data In Higher Level Cache Memory

Abstract

Various aspects include methods for implementing retaining high locality data in a higher level cache memory on a computing device. Various aspects may include receiving a cache access request for a first cache line in the higher level cache memory indicating a locality of the first cache line, determining whether the access request indicates high locality, and setting a high locality indicator of the first cache line in response to determining that the cache access request indicates high locality. Various aspects may include determining whether a lower level cache memory hit counter of a first cache line of a first cache exceeds a lower level cache locality threshold, setting a high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter exceeds the lower level cache locality threshold and resetting the lower level cache memory hit counter of the first cache.

What is claimed is: 
     
         1 . A method of retaining high locality data in a higher level cache memory on a computing device, comprising:
 determining whether a lower level cache memory hit counter of a first cache line of a first cache exceeds a lower level cache locality threshold;   setting a high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the lower level cache locality threshold; and   resetting the lower level cache memory hit counter of the first cache.   
     
     
         2 . The method of  claim 1 , further comprising determining whether promoting the first cache line to having high locality by setting the high locality indicator of the first cache line exceeds a cache set promote threshold,
 wherein setting a high locality indicator of the first cache line comprises setting the high locality indicator of the first cache line in response to determining that promoting the first cache line to having high locality does not exceed the cache set promote threshold.   
     
     
         3 . The method of  claim 2 , further comprising:
 sending a set cache line high locality indicator signal for the first cache line; and   receiving the set cache line high locality indicator signal for the first cache line,   wherein resetting the lower level cache memory hit counter of the first cache comprises resetting the lower level cache memory hit counter of the first cache in response to receiving the set cache line high locality indicator signal for the first cache line.   
     
     
         4 . The method of  claim 2 , further comprising:
 determining whether the lower level cache memory hit counter of the first cache line exceeds a promote replace threshold in response to determining that promoting the first cache line to having high locality exceeds the cache set promote threshold, wherein setting a high locality indicator of the first cache line comprises setting the high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the promote replace threshold;   resetting a high locality indicator of a second cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the promote replace threshold; and   maintaining the high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line does not exceed the promote replace threshold.   
     
     
         5 . The method of  claim 1 , further comprising:
 selecting the first cache line as a victim cache line candidate;   determining whether the high locality indicator of the first cache line is set;   updating a higher level cache hit counter of the first cache line in response to determining that the high locality indicator of the first cache line is set; and   evicting the first cache line in response to determining that the high locality indicator of the first cache line is not set.   
     
     
         6 . The method of  claim 5 , further comprising:
 determining whether the higher level cache hit counter of the first cache line exceeds a replace threshold; and   resetting the higher level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line exceeds the replace threshold.   
     
     
         7 . The method of  claim 1 , further comprising:
 determining whether a higher level cache hit counter of the first cache line exceeds an update threshold;   updating the lower level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line exceeds the update threshold; and   maintaining the lower level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line does not exceed the update threshold.   
     
     
         8 . The method of  claim 1 , further comprising:
 determining whether the high locality indicator of the first cache line is set;   determining whether a higher level cache hit counter of the first cache line exceeds a higher level cache locality threshold in response to determining that the high locality indicator of the first cache line is set; and   updating the higher level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line exceeds the higher level cache locality threshold.   
     
     
         9 . A computing device, comprising:
 a processor;   a higher level cache memory;   a lower level cache memory; and   a cache memory manager communicatively connected to the processor, the higher level cache memory, and the lower level cache memory, and configured to perform operations comprising:
 determining whether a lower level cache memory hit counter of a first cache line of a first cache exceeds a lower level cache locality threshold; 
 setting a high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the lower level cache locality threshold; and 
 resetting the lower level cache memory hit counter of the first cache. 
   
     
     
         10 . The computing device of  claim 9 , wherein the cache memory manager is configured to perform operations further comprising determining whether promoting the first cache line to having high locality by setting the high locality indicator of the first cache line exceeds a cache set promote threshold,
 wherein the cache memory manager is configured to perform operations such that setting a high locality indicator of the first cache line comprises setting the high locality indicator of the first cache line in response to determining that promoting the first cache line to having high locality does not exceed the cache set promote threshold.   
     
     
         11 . The computing device of  claim 10 , wherein the cache memory manager is configured to perform operations further comprising:
 sending a set cache line high locality indicator signal for the first cache line; and   receiving the set cache line high locality indicator signal for the first cache line,   wherein the cache memory manager is configured to perform operations such that resetting the lower level cache memory hit counter of the first cache comprises resetting the lower level cache memory hit counter of the first cache in response to receiving the set cache line high locality indicator signal for the first cache line.   
     
     
         12 . The computing device of  claim 10 , wherein the cache memory manager is configured to perform operations further comprising:
 determining whether the lower level cache memory hit counter of the first cache line exceeds a promote replace threshold in response to determining that promoting the first cache line to having high locality exceeds the cache set promote threshold, wherein setting a high locality indicator of the first cache line comprises setting the high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the promote replace threshold;   resetting a high locality indicator of a second cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the promote replace threshold; and   maintaining the high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line does not exceed the promote replace threshold.   
     
     
         13 . The computing device of  claim 9 , wherein the cache memory manager is configured to perform operations further comprising:
 selecting the first cache line as a victim cache line candidate;   determining whether the high locality indicator of the first cache line is set;   determining whether a higher level cache hit counter of the first cache line exceeds a replace threshold in response to determining that the high locality indicator of the first cache line is set;   updating a higher level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line does not exceed the replace threshold;   resetting the higher level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line exceeds the replace threshold; and   evicting the first cache line in response to determining that the high locality indicator of the first cache line is not set.   
     
     
         14 . The computing device of  claim 9 , wherein the cache memory manager is configured to perform operations further comprising:
 determining whether a higher level cache hit counter of the first cache line exceeds an update threshold;   updating the lower level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line exceeds the update threshold; and   maintaining the lower level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line does not exceed the update threshold.   
     
     
         15 . The computing device of  claim 9 , wherein the cache memory manager is configured to perform operations further comprising:
 determining whether the high locality indicator of the first cache line is set;   determining whether a higher level cache hit counter of the first cache line exceeds a higher level cache locality threshold in response to determining that the high locality indicator of the first cache line is set; and   updating the higher level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line exceeds the higher level cache locality threshold.   
     
     
         16 . A computing device, comprising:
 a higher level cache memory;   a lower level cache memory;   means for determining whether a lower level cache memory hit counter of a first cache line of a first cache exceeds a lower level cache locality threshold;   means for setting a high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the lower level cache locality threshold; and   means for resetting the lower level cache memory hit counter of the first cache.   
     
     
         17 . The computing device of  claim 16 , further comprising means for determining whether promoting the first cache line to having high locality by setting the high locality indicator of the first cache line exceeds a cache set promote threshold,
 wherein the means for setting a high locality indicator of the first cache line comprises means for setting the high locality indicator of the first cache line in response to determining that promoting the first cache line to having high locality does not exceed the cache set promote threshold.   
     
     
         18 . The computing device of  claim 17 , further comprising:
 means for sending a set cache line high locality indicator signal for the first cache line; and   means for receiving the set cache line high locality indicator signal for the first cache line,   wherein the means for resetting the lower level cache memory hit counter of the first cache comprises means for resetting the lower level cache memory hit counter of the first cache in response to receiving the set cache line high locality indicator signal for the first cache line.   
     
     
         19 . The computing device of  claim 17 , further comprising:
 means for determining whether the lower level cache memory hit counter of the first cache line exceeds a promote replace threshold in response to determining that promoting the first cache line to having high locality exceeds the cache set promote threshold, wherein the means for setting a high locality indicator of the first cache line comprises means for setting the high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the promote replace threshold;   means for resetting a high locality indicator of a second cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the promote replace threshold; and   means for maintaining the high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line does not exceed the promote replace threshold.   
     
     
         20 . The computing device of  claim 16 , further comprising:
 means for selecting the first cache line as a victim cache line candidate;   means for determining whether the high locality indicator of the first cache line is set;   means for updating a higher level cache hit counter of the first cache line in response to determining that the high locality indicator of the first cache line is set; and   means for evicting the first cache line in response to determining that the high locality indicator of the first cache line is not set.   
     
     
         21 . The computing device of  claim 20 , further comprising:
 means for determining whether the higher level cache hit counter of the first cache line exceeds a replace threshold; and   means for resetting the higher level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line exceeds the replace threshold.   
     
     
         22 . The computing device of  claim 16 , further comprising:
 means for determining whether a higher level cache hit counter of the first cache line exceeds an update threshold;   means for updating the lower level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line exceeds the update threshold; and   means for maintaining the lower level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line does not exceed the update threshold.   
     
     
         23 . A non-transitory processor-readable storage medium having stored thereon processor-executable instructions configured to cause a processor of a computing device to perform operations comprising:
 determining whether a lower level cache memory hit counter of a first cache line of a first cache exceeds a lower level cache locality threshold;   setting a high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the lower level cache locality threshold; and   resetting the lower level cache memory hit counter of the first cache.   
     
     
         24 . The non-transitory processor-readable storage medium of  claim 23 , wherein the stored processor-executable instructions are further configured to cause a processor of a computing device to perform operations comprising:
 determining whether promoting the first cache line to having high locality by setting the high locality indicator of the first cache line exceeds a cache set promote threshold,   wherein setting a high locality indicator of the first cache line comprises setting the high locality indicator of the first cache line in response to determining that promoting the first cache line to having high locality does not exceed the cache set promote threshold.   
     
     
         25 . The non-transitory processor-readable storage medium of  claim 24 , wherein the stored processor-executable instructions are further configured to cause a processor of a computing device to perform operations comprising:
 sending a set cache line high locality indicator signal for the first cache line; and   receiving the set cache line high locality indicator signal for the first cache line,   wherein resetting the lower level cache memory hit counter of the first cache comprises resetting the lower level cache memory hit counter of the first cache in response to receiving the set cache line high locality indicator signal for the first cache line.   
     
     
         26 . The non-transitory processor-readable storage medium of  claim 24 , wherein the stored processor-executable instructions are further configured to cause a processor of a computing device to perform operations comprising:
 determining whether the lower level cache memory hit counter of the first cache line exceeds a promote replace threshold in response to determining that promoting the first cache line to having high locality exceeds the cache set promote threshold, wherein setting a high locality indicator of the first cache line comprises setting the high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the promote replace threshold;   resetting a high locality indicator of a second cache line in response to determining that the lower level cache memory hit counter of the first cache line exceeds the promote replace threshold; and   maintaining the high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter of the first cache line does not exceed the promote replace threshold.   
     
     
         27 . The non-transitory processor-readable storage medium of  claim 23 , wherein the stored processor-executable instructions are further configured to cause a processor of a computing device to perform operations comprising:
 selecting the first cache line as a victim cache line candidate;   determining whether the high locality indicator of the first cache line is set;   updating a higher level cache hit counter of the first cache line in response to determining that the high locality indicator of the first cache line is set; and   evicting the first cache line in response to determining that the high locality indicator of the first cache line is not set.   
     
     
         28 . The non-transitory processor-readable storage medium of  claim 27 , wherein the stored processor-executable instructions are further configured to cause a processor of a computing device to perform operations comprising:
 determining whether the higher level cache hit counter of the first cache line exceeds a replace threshold; and   resetting the higher level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line exceeds the replace threshold.   
     
     
         29 . The non-transitory processor-readable storage medium of  claim 23 , wherein the stored processor-executable instructions are further configured to cause a processor of a computing device to perform operations comprising:
 determining whether a higher level cache hit counter of the first cache line exceeds an update threshold;   updating the lower level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line exceeds the update threshold; and   maintaining the lower level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line does not exceed the update threshold.   
     
     
         30 . The non-transitory processor-readable storage medium of  claim 23 , wherein the stored processor-executable instructions are further configured to cause a processor of a computing device to perform operations comprising:
 determining whether the high locality indicator of the first cache line is set;   determining whether a higher level cache hit counter of the first cache line exceeds a higher level cache locality threshold in response to determining that the high locality indicator of the first cache line is set; and   updating the higher level cache hit counter of the first cache line in response to determining that the higher level cache hit counter of the first cache line exceeds the higher level cache locality threshold.