Core mapping

Abstract

The disclosed technology is generally directed to peripheral access. In one example of the technology, stored configuration information is read. The stored configuration information is associated with mapping a plurality of independent execution environments to a plurality of peripherals such that the peripherals of the plurality of peripherals have corresponding independent execution environments of the plurality of independent execution environments. A configurable interrupt routing table is programmed based on the configuration information. An interrupt is received from a peripheral. The interrupt is routed to the corresponding independent execution environment based on the configurable interrupt routing table.

1 - 20 . (canceled) 
     
     
         21 . An apparatus, comprising:
 a plurality of processing cores;   a plurality of peripherals; and   a configurable interrupt routing table that selectively maps each of the plurality of peripherals to an individual processing core of the plurality of processing cores, wherein the mapping of each of the plurality of peripherals to the individual processing core is configurable while a lock bit of the apparatus is not set, wherein the mapping of each of the plurality of peripherals to the individual processing core is locked in response to the lock bit of the apparatus being set, and wherein, once locked, the mapping of each of the plurality of peripherals to the individual processing core remains locked until a reboot of the apparatus.   
     
     
         22 . The apparatus of  claim 21 , wherein the configurable interrupt routing table includes a plurality of configuration registers. 
     
     
         23 . The apparatus of  claim 21 , wherein a first processing core of the plurality of processing cores is associated with at least two independent execution environments. 
     
     
         24 . The apparatus of  claim 23 , wherein a first independent execution environment associated with the first processing core is a Secure World operating environment of the first processing core, and wherein a second independent execution environment associated with the first processing core is a Normal World operating environment of the first processing core. 
     
     
         25 . The apparatus of  claim 21 , wherein the configurable interrupt routing table is writable while the lock bit is not set, and the configurable interrupt routing table is not writable while the lock bit is set. 
     
     
         26 . The apparatus of  claim 21 , wherein the plurality of processing cores, the plurality of peripherals, and the configurable interrupt routing table are components on an integrated circuit. 
     
     
         27 . The apparatus of  claim 21 , further comprising:
 a memory that stores the mapping for each of the plurality of peripherals.   
     
     
         28 . The apparatus of  claim 21 , further comprising:
 a routing block that routes interrupts from each of the plurality of peripherals to corresponding processing cores of the plurality of processing cores based on the mappings.   
     
     
         29 . A method, comprising:
 reading stored configuration information that is associated with mapping a plurality of processing cores of a device to a plurality of peripherals of the device such that the peripherals of the plurality of peripherals are assigned to corresponding processing cores of the plurality of cores;   prior to a setting of a lock bit, programming configurable routing based on the configuration information;   setting the lock bit, wherein the configurable routing is locked from after the setting of the lock bit until a reboot of the device; and   routing an interrupt from a peripheral of the plurality of peripherals to a corresponding processing core of the plurality of cores based on the configurable routing.   
     
     
         30 . The method of  claim 29 , wherein the configurable routing employs a configurable data management access routing table. 
     
     
         31 . The method of  claim 29 , wherein the configurable routing includes a configurable interrupt routing table, and wherein the configurable interrupt routing table includes a plurality of configuration registers. 
     
     
         32 . The method of  claim 29 , wherein the setting of the lock bit blocks write access to the configurable routing until the reboot of the device. 
     
     
         33 . The method of  claim 29 , wherein a first processing core of the plurality of processing cores is associated with at least two independent execution environments. 
     
     
         34 . The method of  claim 33 , wherein a first independent execution environment associated with the first processing core is a Secure World operating environment of the first processing core, and wherein a second independent execution environment associated with the first processing core is a Normal World operating environment of the first processing core. 
     
     
         35 . A processor-readable storage medium, having stored thereon processor-executable code that, upon execution by at least one processor, enables actions, the actions comprising:
 reading stored configuration information that is associated with mapping a plurality of processing cores of a device to a plurality of peripherals of the device such that the peripherals of the plurality of peripherals are assigned to corresponding processing cores of the plurality of cores;   programming configurable routing based on the configuration information;   locking the configurable routing by setting a lock bit, wherein the setting of the lock bit locks the configurable routing until the device is rebooted; and   routing an interrupt from a peripheral of the plurality of peripherals to a corresponding processing core of the plurality of cores based on the configurable routing.   
     
     
         36 . The processor-readable storage medium of  claim 35 , wherein the setting of the lock bit prevents write access to the configurable routing. 
     
     
         37 . The processor-readable storage medium of  claim 35 , wherein the configurable routing includes a configurable interrupt routing table with a plurality of configuration registers. 
     
     
         38 . The processor-readable storage medium of  claim 35 , wherein a first independent execution environment associated with a first processing core of the plurality of processing cores is a Secure World operating environment of the first processing core, and wherein a second independent execution environment associated with the first processing core is a Normal World operating environment of the first processing core. 
     
     
         39 . The processor-readable storage medium of  claim 35 , wherein the routing the interrupt from the peripheral to the corresponding processing core is performed by a routing block utilizing the mappings. 
     
     
         40 . The processor-readable storage medium of  claim 35 , wherein programming the configurable routing includes programming a configurable data management access table with the configuration information.