US2020005011A1PendingUtilityA1

Half-bridge Fingeprint Sensing Method

Assignee: CYPRESS SEMICONDUCTOR CORPPriority: Sep 9, 2015Filed: Jul 10, 2019Published: Jan 2, 2020
Est. expirySep 9, 2035(~9.1 yrs left)· nominal 20-yr term from priority
G06K 9/0002G06V 40/1306
59
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Claims

Abstract

Fingerprint detection circuits with common mode noise rejection are described. The Fingerprint detection circuit includes a half-bridge circuit coupled to a receive (RX) electrode of an array of fingerprint detection electrodes and to a buried capacitance that is unalterable by the presence of a conductive object on the array. The fingerprint detection circuit may also include a listener electrode configured to enable common mode noise rejection through a differential input stage of a low noise amplifier (LNA).

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 - 20 . (canceled) 
     
     
         21 . An array of fingerprint detection electrodes comprising:
 a first plurality of electrodes disposed along a first axis; and   a second plurality of electrodes disposed along a second axis, wherein at least one of the second plurality of electrodes is split such that a first portion of the at least one of the second plurality of electrodes and a second portion of the at least one of the second plurality of electrodes are galvanically isolated.   
     
     
         22 . The array of fingerprint detection electrodes of  claim 21 , wherein a first mutual capacitance between the first plurality of electrodes and the first portion of the at least one of the second plurality of electrodes is measured in a first phase, and wherein a second mutual capacitance between the first plurality of electrodes and the at least one of the second portion of the second plurality of electrodes is measured in a second phase. 
     
     
         23 . The array of fingerprint detection electrodes of  claim 22 , wherein the first mutual capacitance forms a first half-bridge circuit with a buried mutual capacitance in the first phase and wherein the second mutual capacitance forms a second half-bridge circuit with the buried mutual capacitance in the second phase. 
     
     
         24 . The array of fingerprint detection electrodes of  claim 21 , further comprising a buried mutual capacitance to form a half-bridge with a mutual capacitance formed at an intersection of at least one of the first plurality of electrodes and the at least one of the second plurality of electrodes. 
     
     
         25 . The array of fingerprint detection electrodes of  claim 21 , wherein the at least one of the second plurality of electrodes that is split is located substantially in the center of the array of fingerprint detection electrodes. 
     
     
         26 . The array of fingerprint detection electrodes of  claim 21 , wherein a portion of the second plurality of electrodes that does not intersect a driven electrode of the first plurality of electrodes is configured to receive common mode noise. 
     
     
         27 . The array of fingerprint detection electrodes of  claim 26 , wherein each of the first and second portions of the at least one of the second plurality of electrodes is selectively coupled to an input of a differential amplifier to reject the common mode noise received by the portion of the second plurality of electrodes that does not intersect the driven electrode of the first plurality of electrodes. 
     
     
         28 . The array of fingerprint detection electrodes of  claim 21 , wherein two or more of the first plurality of electrodes are configured to be driven simultaneously. 
     
     
         29 . A capacitance measurement system comprising:
 an array of fingerprint detection electrodes comprising:
 a first plurality of electrodes disposed along a first axis; and 
 a second plurality of electrodes disposed along a second axis, wherein at least one of the second plurality of electrodes is split such that a first portion of the at least one of the second plurality of electrodes and a second portion of the at least one of the second plurality of electrodes are galvanically isolated. 
   a capacitance measurement circuit coupled to each of the first plurality of electrodes and the second plurality of electrodes, the capacitance measurement circuit comprising a differential amplifier coupled to at least on of the first plurality of electrodes and the at least one of the second plurality of electrodes at a first input and a listener electrode for receiving common mode noise at a second input.   
     
     
         30 . The capacitance measurement system of  claim 29 , wherein a first mutual capacitance between the first plurality of electrodes and the first portion of the at least one of the second plurality of electrodes is measured by the capacitance measurement circuit in a first phase, and wherein a second mutual capacitance between the first plurality of electrodes and the second portion of the at least one of the second plurality of electrodes is measured by the capacitance measurement circuit in a second phase. 
     
     
         31 . The capacitance measurement system comprising of  claim 30 , wherein the first mutual capacitance forms a first half-bridge circuit with a buried mutual capacitance in the first phase and wherein the second mutual capacitance forms a second half-bridge circuit with the buried mutual capacitance in the second phase. 
     
     
         32 . The capacitance measurement system of  claim 29 , further comprising a buried capacitance for forming a half-bridge circuit on the first input of the differential amplifier. 
     
     
         33 . The capacitance measurement system of  claim 29 , wherein a portion of the second plurality of electrodes that does not intersect a driven electrode of the first plurality of electrodes is configured as the listener electrode. 
     
     
         34 . The capacitance measurement system of  claim 29 , wherein the listener electrode is separate from the first plurality of electrodes and the second plurality of electrodes. 
     
     
         35 . A method comprising:
 coupling a first electrode of a first plurality of electrodes to a transmit signal;   coupling a second electrode the a second plurality of electrodes to a first input of a differential amplifier, the second electrode for receiving a receive signal derived from the transmit signal and a mutual capacitance between the first electrode and the second electrode, wherein at least one of the second plurality of electrodes is split such that a first portion of the at least one of the second plurality of electrodes and a second portion of the at least one of the second plurality of electrodes are galvanically isolated;   coupling a listener electrode to a second input of the differential amplifier for receiving common mode noise; and   converting the receive signal to digital value after removing the common mode noise received by the listener electrode.   
     
     
         36 . The method of  claim 35 , wherein the listener electrode is formed by at least one of the second plurality of electrodes. 
     
     
         37 . The method of  claim 35 , wherein the listener electrode is formed by a third electrode not part of the first plurality of electrodes or the second plurality of electrodes. 
     
     
         38 . The method of  claim 35 , wherein the mutual capacitance forms a half-bridge circuit coupled to the first input of the differential amplifier with a buried capacitance. 
     
     
         39 . The method of  claim 38 , wherein the buried capacitance is programmable. 
     
     
         40 . The method of  claim 38 , wherein the buried capacitance is driven by a complementary transmit signal to the transmit signal coupled to the first electrode of the first plurality of electrodes.

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