Low noise trans-impedance amplifiers based on complementary current-injection field-effect transistor devices

Abstract

The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current-injection field-effect transistors (NiFET and PiFET), and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programmed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel/W/L of drain channel).

What is claimed is: 
     
         1 . A trans-impedance amplifier, comprising:
 a. a first complementary pair of a first n-type current-injection field-effect transistor (NiFET) and a first p-type current-injection field-effect transistor (PiFET);   b. a second complementary pair of a second NiFET and a second PiFET;
 wherein each of said NiFETs and PiFETs comprises:
 a source, a drain, a gate, and a diffusion of a corresponding conductivity type of said each of said PiFET and NiFET, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel; 
 wherein said source of said NiFET of said each pair is connected to negative power supply and said source of said PiFET of said each pair is connected to positive power supply, and said drains of said NiFET and said PiFET are connected together to form an output; and 
 wherein said gates of said first complimentary pair and said gates of said second complementary pair are connected with said output of said second complementary pair to for generating a bias voltage output; 
 at least one or both of said diffusion of said first NiFET and said diffusion of said first PiFET receives input current; and 
 said output of said first complementary pair forms a voltage output of said trans-impedance amplifier. 
 
   
     
     
         2 . The trans-impedance amplifier as recited in  claim 1 , wherein, for each said first and said second complementary pairs, said gate of said PiFET and said gate of said NiFET are connected together to form a common gate. 
     
     
         3 . The trans-impedance amplifier as recited in  claim 2 , wherein ratio between width over length of said source channel and width over length of said drain channel of said first and second NiFETs and said first and second PiFETs is adjusted to obtain a suitable input resistance. 
     
     
         4 . The trans-impedance amplifier as recited in  claim 2 , wherein ratio between width over length of said source channel and width over length of said drain channel of said first and second NiFETs and said first and second PiFETs is adjusted to obtain a suitable trans-resistance. 
     
     
         5 . The trans-impedance amplifier as recited in  claim 2 , wherein ratio between width over length of said source channel and width over length of said drain channel of said first and second NiFETs and said first and second PiFETs is adjusted to obtain a suitable gain. 
     
     
         6 . The trans-impedance amplifier as recited in  claim 2  further comprises an output amplifier for amplifying said voltage output of said trans-impedance amplifier. 
     
     
         7 . The trans-impedance amplifier as recited in  claim 6 , wherein said output amplifier comprises a third complementary pair of a third NiFET and a third PiFET, wherein each of said third NiFET and said third PiFET comprises:
 a diffusion of a corresponding conductivity type of said each of said third PiFET and said third NiFET, defining a source channel between a source and said diffusion, and a drain channel between a drain and said diffusion, and a gate capacitively coupled to said source channel and said drain channel;   wherein said source of said third NiFET is connected to negative power supply and said source of said third PiFET is connected to positive power supply, and drains of said third NiFET and said third PiFET are connected together to form an output; and   wherein said gates of said third complimentary pair receives said output of said first complimentary pair.   
     
     
         8 . The trans-impedance amplifier as recited in  claim 7 , wherein said gate of said third PiFET and said gate of said third NiFET are connected together to form a common gate. 
     
     
         9 . The trans-impedance amplifier as recited in  claim 6 , wherein said output amplifier comprises a plurality of complementary pairs of a third NiFET and a third PiFET, wherein
 each of said third NiFET and said third PiFET comprises:   a source, a drain, a gate, and a diffusion of a corresponding conductivity type of said each of said third PiFET and said third NiFET, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel;   wherein said source of said third NiFET is connected to negative power supply and said source of said third PiFET is connected to positive power supply, and drains of said third NiFET and said third PiFET are connected together to form an output of each of said plurality of complementary pairs;   wherein said gates of a subsequent one of said plurality of complementary pairs receives said output of a prior one of said plurality of complementary pairs; and   wherein said gates of said first one of said plurality of complementary pairs receives said output of said first complimentary pair.   
     
     
         10 . The trans-impedance amplifier as recited in  claim 9 , wherein said gate of said third PiFET and said gate of said third NiFET are connected together to form a common gate. 
     
     
         11 . The trans-impedance amplifier as recited in  claim 9 , wherein said output of said second one of said plurality of complementary pairs is further capacitively coupled to said diffusion of said third NiFET of said first one of said plurality of complementary pairs and to said diffusion of said third PiFET of said first one of said plurality of complementary pairs. 
     
     
         12 . The trans-impedance amplifier as recited in  claim 11 , wherein said output amplifier further comprises a feedforward amplifier receiving said output of said first complementary pair and coupling an output of said feedforward amplifier with said output of said last one of said plurality of complementary pairs. 
     
     
         13 . The trans-impedance amplifier as recited in  claim 12 , wherein said feedforward amplifier is a fourth complementary pair of a fourth NiFET and a fourth PiFET, each of said fourth NiFET and said fourth PiFET comprises:
 a diffusion of a corresponding conductivity type of said each of said fourth PiFET and said fourth NiFET, defining a source channel between a source and said diffusion, and a drain channel between a drain and said diffusion, and a gate capacitively coupled to said source channel and said drain channel;   wherein said source of said fourth NiFET is connected to negative power supply and said source of said fourth PiFET is connected to positive power supply, and drains of said fourth NiFET and fourth third PiFET are connected together to form said output of said feedforward amplifier;   wherein said gates of said fourth complementary pair receives said output of said last one of said plurality of complimentary pairs.   
     
     
         14 . The trans-impedance amplifier as recited in  claim 13 , wherein said gate of said fourth PiFET and said gate of said fourth NiFET are connected together to form a common gate. 
     
     
         15 . A differential amplifier for amplifying difference between a first input and a second input, each of said first and second inputs having negative and positive polarity inputs, comprising:
 a. a first complementary pair of a first n-type current-injection field-effect transistor (NiFET) and a first p-type current-injection field-effect transistor (PiFET);   b. a second complementary pair of a second NiFET and a second PiFET; and   c. a third complementary pair of a third NiFET and a third PiFET;   wherein each of said NiFETs and PiFETs comprises:
 a source, a drain, a gate, and a diffusion of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel; 
 wherein said source of said NiFET of said each complimentary pair is connected to negative power supply and said source of said PiFET of said each pair is connected to positive power supply, and drains of said NiFET and said PiFET of said each complimentary pair are connected together to form an output; and 
 wherein said gates of said first complimentary pair, said gate of said second complementary pair and said gates of said third complementary pair are connected with said output of said second complementary pair for generating a bias voltage output; 
 said diffusion of said third PiFET receives said negative polarity input of said first input; 
 said diffusion of said first PiFET receives said positive polarity input of said first input; 
 said diffusion of said third NiFET receives said negative polarity input of said second input; 
 said diffusion of said first NiFET receives said positive polarity input of said second input; and 
 said output of said first complementary pair forms output of said differential amplifier. 
   
     
     
         16 . The differential amplifier as recited in  claim 15 , wherein, for said each complementary pair, said gate of said PiFET and said gate of said NiFET are connected together to form a common gate. 
     
     
         17 . An optical signal receiver, comprising:
 a. a photodiode comprising a cathode and anode;   b. a reference for said photodiode, comprising cathode and anode;   c. a differential current amplifier, comprising a first, second and third complementary pairs of a n-type current-injection field-effect transistor (NiFET) and a p-type current-injection field-effect transistor (PiFET);   wherein each of said NiFETs and PiFETs comprises:
 a source, a drain, a gate, and a diffusion of a corresponding conductivity type of said each of said PiFET and NiFET, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel; 
 said source of said NiFET is connected to negative power supply and said source of said PiFET is connected to positive power supply, and drains of said NiFET and said PiFET are connected together to form an output; 
 said gates of said first complimentary pair and said gates of said second complementary pair are connected with said output of said second complementary pair, and received by said gates of said third complementary pair; 
 said diffusion of said PiFET of said first complementary pair receives said cathode of said photodiode; 
 said diffusion of said PiFET of said third complementary pair receives said cathode of said reference; 
 said diffusion of said NiFET of said first complementary pair receives said anode of said reference; 
 said diffusion of said NiFET of said third complementary pair receives said anode of said photodiode; and 
 said output of said first complementary pair forms a voltage output, and said output of said third complementary pair provides a bias voltage for said voltage output. 
   
     
     
         18 . The optical signal receiver as recited in  claim 17 , wherein, for each complementary pair, said gate of said PiFET and said gate of said NiFET are connected together to form a common gate. 
     
     
         19 . An wireless signal transceiver, comprising:
 a. a wireless antenna;   b. a differential current amplifier, comprising a first, second and third complementary pairs of a n-type current-injection field-effect transistor (NiFET) and a p-type current-injection field-effect transistor (PiFET);   wherein each of said NiFETs and PiFETs comprises:
 a source, a drain, a gate, and a diffusion of a corresponding conductivity type of said each of said PiFET and NiFET, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel; 
 said source of said NiFET is connected to negative power supply and said source of said PiFET is connected to positive power supply, and drains of said NiFET and said PiFET are connected together to form an output; 
 said gates of said first complimentary pair and said gates of said second complementary pair are connected with said output of said second complementary pair, and received by said gates of said third complementary pair; 
 said diffusion of said PiFET of said first complementary pair receives said antenna; 
 said diffusion of said PiFET of said third complementary pair is resistively coupled with said antenna; 
 said diffusions of said NiFET of said first, second and third complementary pairs are connected together to receive current for gain control; 
 said output of said first complementary pair forms a voltage output, said output of said second complementary pair provides an analog ground for said voltage output, and said output of said third complementary pair provides a bias voltage for said voltage output. 
   
     
     
         20 . The wireless signal transceiver as recited in  claim 19 , wherein, for each complementary pair, said gate of said PiFET and said gate of said NiFET are connected together to form a common gate. 
     
     
         21 . A gain controllable trans-impedance amplifier, comprising:
 a. a positive current input, and a negative current input,   b. a positive voltage output, and a negative voltage output;   c. a bias output;   d. a first complementary pair of a first n-type current-injection field-effect transistor (NiFET) and a first p-type current-injection field-effect transistor (PiFET);   e. a second complementary pair of a second NiFET and a second PiFET; and   f. a third complementary pair of a third NiFET and a third PiFET;   wherein each of said NiFETs and PiFETs comprises:   a source, a drain, a gate, and a diffusion of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel;   wherein said source of said NiFET of said each complimentary pair is connected to negative power supply and said source of said PiFET of said each pair is connected to positive power supply, and drains of said NiFET and said PiFET of said each complimentary pair are connected together to form an output; and   wherein   said diffusion of said third NiFET receives said negative current input;   said diffusion of said first NiFET receives said positive current input;   said gates of said first complimentary pair, said gates of said second complementary pair and said gates of said third complementary pair are connected with said output of said second complementary pair for said bias voltage output;   said output of said first complementary pair is connected to said positive voltage output;   said output of said third complementary pair is connected to said negative voltage output;   wherein said gain controllable trans-impedance amplifier further comprises gain control switch for selectively connecting said negative voltage supply to said diffusions of said first, second and third PiFETs.   
     
     
         22 . The gain controllable trans-impedance amplifier as recited in  claim 21 , wherein, for each complementary pair, said gate of said PiFET and said gate of said NiFET are connected together to form a common gate. 
     
     
         23 . An isolator circuit, comprising:
 a. a differential current amplifier, comprising a first, second and third complementary pairs of a n-type current-injection field-effect transistor (NiFET) and a p-type current-injection field-effect transistor (PiFET);   wherein each of said NiFETs and PiFETs comprises:
 a source, a drain, a gate, and a diffusion of a corresponding conductivity type of said each of said PiFET and NiFET, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and a gate capacitively coupled to said source channel and said drain channel, and said gate is capacitively coupled to said source channel and drain channel; 
 said source of said NiFET is connected to negative power supply and said source of said PiFET is connected to positive power supply, and drains of said NiFET and said PiFET are connected together to form an output; 
   wherein said gates of said first complimentary pair and said gates of said second complementary pair are connected with said output of said second complementary pair, and received by said gates of said third complementary pair;   said diffusion of said PiFET of said first complementary pair is coupled to an input and output;   said diffusion of said PiFET of said third complementary pair is resistively coupled with said input and output;   said diffusions of said NiFET of said first, second and third complementary pairs are connected together to receive current for gain control;   said output of said first complementary pair forms a voltage output, said output of said second complementary pair provides an analog ground for said voltage output, and said output of said third complementary pair provides an bias voltage for said voltage output.   
     
     
         24 . The isolator circuit as recited in  claim 23 , wherein, for each complementary pair, said gate of said PiFET and said gate of said NiFET are connected together to form a common gate. 
     
     
         25 . A multiple input and output circulator circuit coupled to a plurality of input and output terminals, comprising:
 a. a plurality of differential current amplifiers, each differential current amplifier comprising a first, second and third complementary pairs of a n-type current-injection field-effect transistor (NiFET) and a p-type current-injection field-effect transistor (PiFET);
 each of said NiFETs and PiFETs comprises:
 i. a source, a drain, a gate, and a diffusion of a corresponding conductivity type of said each of said PiFET and NiFET, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and a gate capacitively coupled to said source channel and said drain channel, and said gate is capacitively coupled to said source channel and drain channel; 
 ii. said source of said NiFET is connected to negative power supply and said source of said PiFET is connected to positive power supply, and drains of said NiFET and said PiFET are connected together to form an output; 
 
 wherein said gates of said first complimentary pair and said gates of said second complementary pair are connected with said output of said second complementary pair, and received by said gates of said third complementary pair; 
 said diffusion of said PiFET of said first complementary pair forms a non-inverting positive current input; 
 said diffusion of said PiFET of said third complementary pair forms an inverting positive current input; 
 said diffusion of said NiFET of said first complementary pair forms a non-inverting negative current input; 
 said diffusion of said NiFET of said third complementary pair forms an inverting negative current input; 
 said output of said first complementary pair forms a non-inverting voltage output, said output of said second complementary pair provides an analog ground for said voltage output, and said output of said third complementary pair provides an bias voltage for said voltage output; 
   wherein said non-inverting voltage output of a previous one of said plurality of said differential current amplifiers is capacitively and resistively coupled to said non-inverting and said inverting positive current inputs of a subsequent one of plurality of said differential current amplifiers; and   said non-inverting voltage output of a last one of said plurality of said differential current amplifiers is capacitively and resistively coupled to said non-inverting and said inverting positive current inputs of a first one of said plurality of said differential current amplifiers;   a corresponding one of said plurality of said input and output terminals is coupled to said inverting positive current input of a corresponding one of said plurality of said differential current amplifiers.   
     
     
         26 . The multiple input and output circulator circuit coupled to a plurality of input and output terminals as recited in  claim 25 , wherein, for each complementary pair, said gate of said PiFET and said gate of said NiFET are connected together to form a common gate. 
     
     
         27 . A latch current comparator, comprising:
 a. a differential amplifier for amplifying difference between a first input and a second input, each of said first and second inputs having negative and positive polarity inputs, comprising:
 i. a first complementary pair of a first n-type current-injection field-effect transistor (NiFET) and a first p-type current-injection field-effect transistor (PiFET); 
 ii. a second complementary pair of a second NiFET and a second PiFET; and 
 iii. a third complementary pair of a third NiFET and a third PiFET; and 
   b. a comparator, comprising:
 i. a fourth complementary pair of a fourth NiFET and a fourth PiFET; 
 ii. a fifth complementary pair of a fifth NiFET and a fifth PiFET; 
 iii. a plurality of switches operable on a control signal that alternates enable and setup phases; 
 iv. a first capacitor and a second capacitor, each has a first terminal and a second terminal; 
   wherein each of said NiFETs and PiFETs comprises:
 a source, a drain, a gate, and a diffusion of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel; 
 wherein said source of said NiFET of said each complimentary pair is connected to negative power supply and said source of said PiFET of said each pair is connected to positive power supply, and drains of said NiFET and said PiFET of said each complimentary pair are connected together to form an output; and 
 wherein said gates of said first complimentary pair, said gates of said second complementary pair and said gates of said third complementary pair are connected with said output of said second complementary pair for generating a bias voltage output; 
 said diffusion of said third PiFET receives said negative polarity input of said first input; 
 said diffusion of said first PiFET receives said positive polarity input of said first input; 
 said diffusion of said third NiFET receives said negative polarity input of said second input; 
 said diffusion of said first NiFET receives said positive polarity input of said second input; and 
 said output of said first complementary pair forms positive voltage output of said differential amplifier; 
 said output of said third complementary pair forms negative voltage output of said differential amplifier; 
   wherein said output of said fourth complementary pair is capacitively coupled to said input of said fifth complementary pair through said second capacitor;   said second terminal of said first capacitor is coupled to said input of said fourth complementary pair;   during said setup phase of said control signal, said plurality of switches cause said positive voltage output of said differential amplifier to be coupled with said first terminal of said first capacitor, said fourth complementary pair to be self-biased by connecting said output of said fourth complementary pair to said input of said fourth complementary pair, and said fifth complementary pair to be self-biased by connecting said output of said fifth complementary pair to said input of said fifth complementary pair;
 during said enable phase of said control signal, said plurality of switches cause said negative voltage output of said differential amplifier to be coupled to said first terminal of said first capacitor, and said output of said fifth complementary pair to said input of said fourth complementary pair. 
   
     
     
         28 . The latch current comparator as recited in  claim 27 , wherein, for each complementary pair, said gate of said PiFET and said gate of said NiFET are connected together to form a common gate. 
     
     
         29 . An NAND logic gate, comprising a p-type current-injection field-effect transistor (PiFET);
 wherein said PiFET comprises:
 a source, a drain, a gate, and a diffusion, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel; 
 wherein said source is connected to positive power supply; and 
 said gate receives a bias voltage; 
   wherein said diffusion receives a plurality of current inputs for subtracting said plurality of current inputs and causes said drain to provide an output current.   
     
     
         30 . An NOR logic gate, comprising an n-type current-injection field-effect transistor (NiFET);
 wherein said NiFET comprises:
 a source, a drain, a gate, and a diffusion, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel; 
 wherein said source is connected to negative power supply; and 
 said gate receive a bias voltage; 
   wherein said diffusion receives a plurality of current inputs for summing said plurality of current inputs and causes said drain to provide an output current.   
     
     
         31 . A current bypass controller, comprising:
 a. a complementary pair of an n-type current-injection field-effect transistor (NiFET) and a p-type current-injection field-effect transistor (PiFET);
 wherein each of said NiFET and PiFET comprises:
 i. a source, a drain, a gate, and a diffusion, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel;
 wherein said source of said NiFET is connected to negative power supply and said source of said PiFET is connected to positive power supply, and drains of said NiFET and said PiFET are connected together to form an output; and 
 
 
 wherein said gates receives an input; 
   b. a transistor of N or P-type comprising a source, a drain and a gate, wherein said diffusion of PiFET is received at said source of said transistor of P-type or at said drain of said transistor of N-type, and said diffusion of NiFET is received at said source of said transistor of N-type or at said drain of said transistor of P-type;   wherein said gate of said transistor form an output of said current bypass controller.