Radio-frequency switches with distorter arms and voltage buffers

Abstract

Disclosed herein are systems and methods for reducing intermodulation distortion (IMD) in switches using distorter circuits and voltage buffers. A switch circuit can include a switch arm with a stack of field-effect transistors (FETs), a distorter arm that is configured to act as a compensation circuit to compensate for non-linearities in the switch arm, and a voltage buffer that is configured to protect the distorter arm from large voltage swings when transitioning between ON and OFF states. The gate width of the distorter arm can be orders of magnitude smaller than the gate widths of the switch FETs. The gate width of the voltage buffer FETs can be larger than the distorter arm and smaller than the switch arm. The distorter arm is configured to compensate for the non-linearity effect generated by the switch arm.

What is claimed is: 
     
         1 . A radio-frequency (RF) switch comprising:
 a switch arm having a set of switch field-effect transistors (FETs) coupled in series and disposed between a first node and a second node, individual switch FETs of the set of switch FETs having a switch FET gate width;   a distorter arm coupled in parallel to the switch arm, the distorter arm having a distorter FET with a distorter FET gate width, the distorter arm configured to compensate a non-linearity effect generated by the set of switch FETs; and   a voltage buffer coupled in series with the distorter arm and in parallel with the switch arm, the voltage buffer having a set of buffer FETs coupled in series, individual buffer FETs of the set of buffer FETs having a buffer FET gate width that is larger than the distorter FET gate width and smaller than the switch FET gate width, the voltage buffer configured to protect the distorter arm from large voltage swings as the RF switch transitions between ON and OFF states.   
     
     
         2 . The RF switch of  claim 1  wherein the distorter FET gate width is smaller than about 10 μm and the switch FET gate width is larger than about 1 mm. 
     
     
         3 . The RF switch of  claim 2  wherein the buffer FET gate width is about 200 mm. 
     
     
         4 . The RF switch of  claim 1  wherein the distorter FET gate width is about 500 times smaller than the switch FET gate width. 
     
     
         5 . The RF switch of  claim 1  wherein the set of switch FETs includes at least 12 FETs. 
     
     
         6 . The RF switch of  claim 5  wherein the set of buffer FETs includes at least 12 FETs. 
     
     
         7 . The RF switch of  claim 6  wherein the distorter arm includes a single distorter FET. 
     
     
         8 . The RF switch of  claim 1  wherein, in an ON state, the voltage buffer, the switch arm, and the distorter arm are configured to be in an ON state. 
     
     
         9 . The RF switch of  claim 8  wherein, in an OFF state, the voltage buffer and the switch arm are configured to be in an OFF state and the distorter arm is configured to be in an ON state. 
     
     
         10 . The RF switch of  claim 1  wherein the distorter arm is configured to generate third-order intermodulation distortion to reduce a non-linearity effect generated by the set of switch FETs. 
     
     
         11 . The RF switch of  claim 1  further comprising a control module configured to control operation of the switch arm, the distorter arm, and the voltage buffer. 
     
     
         12 . The RF switch of  claim 1  further comprising a biasing circuit configured to bias the distorter arm and the voltage buffer. 
     
     
         13 . The RF switch of  claim 12  wherein the biasing circuit is not configured to bias the switch arm. 
     
     
         14 . The RF switch of  claim 12  wherein the biasing circuit is configured to provide a buffer gate voltage to gate terminals of the set of buffer FETs. 
     
     
         15 . The RF switch of  claim 12  wherein the biasing circuit is configured to provide a distorter gate voltage to a gate terminal of the distorter FET. 
     
     
         16 . The RF switch of  claim 12  wherein the biasing circuit includes a current source to drive current to the distorter arm. 
     
     
         17 . The RF switch of  claim 1  wherein the set of switch FETs comprise silicon-on-insulator (SOI) FETs. 
     
     
         18 . A radio-frequency (RF) switch module comprising:
 a packaging substrate configured to receive a plurality of components;   a semiconductor die mounted on the packaging substrate, the semiconductor die including a set of switch field-effect transistors (FETs) in a switch arm, the set of switch FETs each having a switch FET gate width;   a distorter arm mounted on the packaging substrate coupled in parallel with the switch arm, the distorter arm having a distorter FET with a distorter FET gate width, the distorter arm configured to compensate a non-linearity effect generated by the switch arm; and   a voltage buffer mounted on the packaging substrate coupled in parallel with the switch arm and in series with the distorter arm, the voltage buffer including a set of buffer FETs each having a buffer FET gate width such that the buffer FET gate width is greater than the distorter FET gate width and less than the switch FET gate width.   
     
     
         19 . The RF switch module of  claim 18  wherein the distorter arm and the voltage buffer are implemented on the semiconductor die. 
     
     
         20 . A wireless device comprising:
 a transceiver configured to process radio-frequency (RF) signals;   an antenna in communication with the transceiver configured to facilitate transmission of an amplified RF signal;   a power amplifier connected to the transceiver and configured to generate the amplified RF signal; and   a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna, the switch including a set of switch field-effect transistors (FETs) in a switch arm, the set of switch FETs each having a switch FET gate width; the switch further including a distorter arm mounted on the packaging substrate coupled in parallel with the switch arm, the distorter arm having a distorter FET with a distorter FET gate width, the distorter arm configured to compensate a non-linearity effect generated by the switch arm; and the switch further including a voltage buffer mounted on the packaging substrate coupled in parallel with the switch arm and in series with the distorter arm, the voltage buffer including a set of buffer FETs each having a buffer FET gate width such that the buffer FET gate width is greater than the distorter FET gate width and less than the switch FET gate width.