Super-saturation current field effect transistor and trans-impedance mos device

Abstract

The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuits.

What is claimed is: 
     
         1 . A field effect transistor, comprising:
 a semiconductor substrate of a conductivity type, comprising:
 a source, a drain, a diffusion, a first gate, and a second gate; 
 a source channel is defined between said source and diffusion, 
 a drain channel is defined between said drain and diffusion; 
   wherein said first gate is capacitively coupled to said source channel; and   said second gate is capacitively coupled to said drain channel.   
     
     
         2 . The field effect transistor as recited in  claim 1 , wherein a trans-resistance of the field effect transistor is established by a ratio of:
 a. the ratio of the width and the length of the drain channel segment; and   b. the ratio of the width and the length of the source channel segment.   
     
     
         3 . The field effect transistor as recited in  claim 2 , wherein a current is applied at said diffusion is converted to a voltage by said trans-resistance. 
     
     
         4 . The field effect transistor as recited in  claim 1 , wherein said conductive type is N-type. 
     
     
         5 . The field effect transistor as recited in  claim 1 , wherein said conductive type is P-type. 
     
     
         6 . A composite transistor, comprising:
 N-type field effect transistor (NxiFET) and a P-type field effect transistor (PxiFET), each comprising:
 a semiconductor substrate of a corresponding conductivity type, comprising:
 a source, a drain, a diffusion, a first gate, and a second gate; 
 a source channel is defined between said source and diffusion, 
 a drain channel is defined between said drain and diffusion; 
 said first gate is capacitively coupled to said source channel; and 
 said second gate is capacitively coupled to said drain channel; 
 
   wherein
 said source of said NxiFET receives negative supply voltage; 
 said source of said PxiFET receives positive supply voltage; 
 said drain of said NxiFET and said drain of said PxiFET are coupled together to form an output; and 
 the second gate of said NxiFET and the second gate of said PxiFET are coupled together to form an input. 
   
     
     
         7 . A focal plane array read out, comprising:
 a P-type current field effect transistor (PiFET) and an N-type current field effect transistor (NxiFET),
 said PiFET comprising a semiconductor substrate of a corresponding conductivity type, comprising:
 a source, a drain, a diffusion, and a gate; 
 a source channel is defined between said source and said diffusion, 
 a drain channel is defined between said drain and said diffusion; 
 said gate is capacitively coupled to said source channel and said drain channel; 
 
 said NxiFET comprising a semiconductor substrate of a corresponding conductivity type, comprising:
 a source, a drain, a diffusion, a first gate, and a second gate; 
 a source channel is defined between said source and diffusion, 
 a drain channel is defined between said drain and diffusion; 
 said first gate is capacitively coupled to said source channel; and 
 said second gate is capacitively coupled to said drain channel; 
 
 wherein said drain of said PiFET and said drain of said NxiFET are connected together to form an output; 
 said source of said PiFET is coupled to a positive power supply; 
 said source of said NxiFET is coupled to a negative power supply; 
 said diffusion of said PiFET receives a gain control signal; 
 said gate of said PiFET receives a bias voltage; 
   a switch operable by a select signal comprising first and second phases; and   a capacitor for storing a pixel voltage from a photodiode, comprising a first and second terminals, said second terminal of said capacitor is coupled to said negative power supply and said first terminal of said capacitor receives said pixel voltage from said photodiode, and said first terminal is coupled to said second gate of said NxiFET;   wherein, during said first phase of said select signal, said switch causes said bias voltage to couple with said first gate of said NxiFET;   during said second phase of said select signal causes said negative power supply to couple with said first gate.   
     
     
         8 . A latch current comparator, comprising:
 a differential amplifier for amplifying difference between a first input and a second input, each of said first and second inputs comprising negative and positive polarity inputs, comprising:
 a first complementary pair of a first n-type current field-effect transistor (NiFET) and a first p-type current field-effect transistor (PiFET); 
 a second complementary pair of a second NiFET and a second PiFET; and 
 a third complementary pair of a third NiFET and a third PiFET; and 
   a comparator, comprising:
 a fourth complementary pair of a fourth NiFET and a fourth PiFET; 
 a fifth complementary pair of a fifth NiFET and a fifth PiFET; 
 a plurality of switches operable on a control signal that alternates enable and setup phases; 
 a first capacitor and a second capacitor, each has a first terminal and a second terminal; 
   wherein each of said NiFETs and PiFETs comprises:
 a source, a drain, a gate, and a diffusion, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, 
 and said gate is capacitively coupled to said source channel and said drain channel; 
   wherein said source of said NiFET of said each complimentary pair is connected to negative power supply and said source of said PiFET of said each pair is connected to positive power supply, and drains of said NiFET and said PiFET of said each complimentary pair are connected together to form an output; and   wherein said gates of said first complimentary pair, said gates of said second complementary pair and said gates of said third complementary pair are connected with said output of said second complementary pair for generating a bias voltage output;   said diffusion of said third PiFET receives said negative polarity input of said first input;   said diffusion of said first PiFET receives said positive polarity input of said first input;   said diffusion of said third NiFET receives said negative polarity input of said second input;   said diffusion of said first NiFET receives said positive polarity input of said second input; and   said output of said first complementary pair forms positive voltage output of said differential amplifier;   said output of said third complementary pair forms negative voltage output of said differential amplifier;   wherein said output of said fourth complementary pair is capacitively coupled to said input of said fifth complementary pair through said second capacitor;   said second terminal of said first capacitor is coupled to said input fo said fourth complementary pair;   during said setup phase of said control signal, said plurality of switches cause said positive voltage output of said differential amplifier to be coupled with said first terminal of said first capacitor, said fourth complementary pair to be self-biased by connecting said output of said fourth complementary pair to said input of said fourth complementary pair, and said fifth complementary pair to be self-biased by connecting said output of said fifth complementary pair to said input of said fifth complementary pair;   during said enable phase of said control signal, said plurality of switches cause said negative voltage output of said differential amplifier to be coupled to said first terminal of said first capacitor, and said output of said fifth complementary pair to said input of said fourth complementary pair.   
     
     
         9 . The latch current comparator recited in  claim 8 , wherein, for said each complimentary pair, said gate of said PiFET and said gate of said NiFET are connected together to form a common gate.