Semiconductor device having symmetric conductive interconnection patterns

Abstract

A semiconductor device may include a lower interlayer dielectric layer, a conductive interconnection pattern structure and a filling pattern over the lower interlayer dielectric layer, and a top interlayer dielectric layer over the conductive interconnection pattern structure and the filling patterns. Each of the conductive interconnection pattern structure may include an intermediate pattern in the center thereof, a first conductive interconnection pattern on a first side surface of the intermediate pattern, and a second conductive interconnection pattern on a second side surface of the intermediate pattern. The first conductive interconnection pattern and the second conductive interconnection pattern may have a symmetrical structure to each other.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a lower interlayer dielectric layer;   a conductive interconnection pattern structure and a filling pattern over the lower interlayer dielectric layer; and   an upper interlayer dielectric layer over the conductive interconnection pattern structure and the filling pattern,   wherein the conductive interconnection pattern structure includes:
 an intermediate pattern in the center thereof; 
 a first conductive interconnection pattern on a first side surface of the intermediate pattern; and 
 a second conductive interconnection pattern on a second side surface of the intermediate pattern, 
 wherein the first conductive interconnection pattern and the second conductive interconnection pattern have a symmetrical structure to each other. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first conductive interconnection pattern has a first side surface that is vertically flat and a second side surface that is inclined and rounded. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the second side surface of the first conductive interconnection pattern has a relatively small top horizontal width and a relatively large bottom horizontal width. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the second conductive interconnection pattern has a first side surface that is vertically flat and a second side surface that is rounded. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the second side surface of the second conductive interconnection pattern has a relatively small top horizontal width and a relatively large bottom horizontal width. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the first conductive interconnection pattern and the second conductive interconnection pattern each include a metal. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the intermediate pattern has first and second side surfaces that are vertically flat. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the intermediate pattern includes a dielectric material. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the filling pattern has a relatively small bottom horizontal width and a relatively large top horizontal width. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the filling pattern has negatively rounded side surfaces. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the filling pattern includes a dielectric material. 
     
     
         12 . The semiconductor device of  claim 1 , wherein each of the conductive interconnection pattern structure further includes:
 a first barrier pattern disposed between the intermediate pattern and the first conductive interconnection pattern; and   a second barrier pattern disposed between the intermediate pattern and the second conductive interconnection pattern.   
     
     
         13 . The semiconductor device of  claim 12 , wherein the first barrier pattern includes a vertical portion between the first side surface of the intermediate pattern and the first side surface of the first conductive interconnection pattern and a horizontal portion between a bottom surface of the first conductive interconnection pattern and a top surface of the lower interlayer dielectric layer. 
     
     
         14 . The semiconductor device of  claim 12 , wherein the second barrier pattern includes a vertical portion between the second side surface of the intermediate pattern and the first side surface of the second conductive interconnection pattern and a horizontal portion between a bottom surface of the second conductive interconnection pattern and a top surface of the lower interlayer dielectric layer. 
     
     
         15 . The semiconductor device of  claim 12 , wherein the first and second barrier patterns include titanium nitride. 
     
     
         16 . The semiconductor device of  claim 12 ,
 wherein the second side surface of the first conductive interconnection pattern and the second side surface of the second conductive interconnection pattern abut on both side surfaces of each of the filling pattern, respectively,   the first side surfaces and bottom surfaces of the first conductive interconnection pattern abut on the first barrier pattern, and   the first side surfaces and bottom surfaces of the second conductive interconnection pattern abut on the second barrier pattern.   
     
     
         17 . The semiconductor device of  claim 1 , wherein the first and second conductive interconnection patterns and the filling pattern are coplanar with one another. 
     
     
         18 . The semiconductor device of  claim 1 , further comprising a stopper layer between the lower interlayer dielectric layer and the filling pattern,
 wherein the stopper layer includes a harder dielectric material than included in the lower interlayer dielectric layer and the filling pattern.   
     
     
         19 . The semiconductor device of  claim 1 , further comprising a capping layer between the filling pattern and the upper interlayer dielectric layer,
 wherein the capping layer includes a harder dielectric material than included in the filling pattern and the upper interlayer dielectric layer.   
     
     
         20 . The semiconductor device of  claim 1 , wherein an average horizontal width of the intermediate pattern, a maximum horizontal width of the conductive interconnection pattern structure and a minimum horizontal width of the filling pattern are substantially equal to one another. 
     
     
         21 . A method for fabricating a semiconductor device, comprising:
 forming a stopper layer;   forming an intermediate pattern material layer over the stopper layer;   forming a plurality of first preliminary intermediate patterns by patterning the intermediate pattern material layer;   forming a plurality of second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns;   forming a conductive material layer to cover the second preliminary intermediate patterns;   forming a plurality of preliminary conductive interconnection patterns by patterning the conductive material layer;   forming a filling layer between the preliminary conductive interconnection patterns; and   forming a plurality of intermediate patterns, a plurality of conductive interconnection patterns and a plurality of filling patterns by removing top portions of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns.   
     
     
         22 . The method of  claim 21 , wherein vertical heights and horizontal widths of the first preliminary intermediate patterns are greater than vertical heights and horizontal widths of the second preliminary intermediate patterns. 
     
     
         23 . The method of  claim 21 , wherein the conductive interconnection patterns include left conductive interconnection patterns formed on the left of the intermediate patterns and right conductive interconnection patterns formed on the right of the intermediate patterns,
 wherein each of the left conductive interconnection patterns includes a flat right side surface and a rounded left side surface, and   each of the right conductive interconnection patterns includes a flat left side surface and a rounded right side surface.   
     
     
         24 . The method of  claim 23 , wherein each of the intermediate patterns includes both flat side surfaces, and
 each of the filling patterns includes both side surfaces that are rounded to have negative slopes where a bottom portion is narrow and a top portion is wide.   
     
     
         25 . The method of  claim 23 , wherein the sum of a horizontal width of each left conductive interconnection pattern and a horizontal width of each intermediate pattern is equal to a horizontal width of each first preliminary intermediate pattern. 
     
     
         26 . The method of  claim 23 , wherein the sum of a horizontal width of each right conductive interconnection pattern and a horizontal width of each intermediate pattern is equal to a horizontal width of each first preliminary intermediate pattern. 
     
     
         27 . The method of  claim 23 , wherein the sum of a horizontal width of each left conductive interconnection pattern and a horizontal width of each right conductive interconnection pattern is equal to a horizontal width of each first preliminary intermediate pattern. 
     
     
         28 . The method of  claim 21 , wherein the intermediate pattern material layer and the filling layer include at least one of silicon oxide, silicon nitride, or silicon oxynitride, or any combination thereof. 
     
     
         29 . The method of  claim 21 , wherein the conductive material layer includes a metal. 
     
     
         30 . The method of  claim 21 , wherein the forming of the preliminary conductive interconnection patterns by patterning the conductive material layer includes performing an etch-back process, and
 the plurality of preliminary conductive interconnection patterns are formed by separating the conductive material layer.   
     
     
         31 . The method of  claim 21 , wherein the removing of a top portion of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns includes performing a Chemical Mechanical Polishing (CMP) process, and
 wherein a top surface of each of the intermediate patterns, the conductive interconnection patterns and the filling patterns are coplanar with one another.   
     
     
         32 . The method of  claim 21 , further comprising:
 forming a barrier material layer between the second preliminary intermediate patterns and the conductive material layer; and   forming a plurality of barrier patterns which are physically separate, by patterning the barrier material layer after the forming of the preliminary conductive interconnection patterns.   
     
     
         33 . A method for fabricating a semiconductor device, comprising:
 forming a lower interlayer dielectric layer over a substrate;   forming a stopper layer over the lower interlayer dielectric layer;   forming first preliminary intermediate patterns over the stopper layer;   forming second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns;   forming preliminary conductive interconnection patterns to cover top surfaces and both side surfaces of the second preliminary intermediate patterns;   forming a filling layer between the preliminary conductive interconnection patterns;   forming intermediate patterns with side surfaces, conductive interconnection patterns on the side surfaces of the intermediate patterns and filling patterns between the conductive interconnection patterns by removing a top portion of each of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns;   forming a capping layer over the intermediate patterns, the conductive interconnection patterns and the filling patterns; and   forming an upper interlayer dielectric layer over the capping layer.   
     
     
         34 . The method of  claim 33 , wherein the forming of the second preliminary intermediate patterns includes partially removing portions from the top and both sides of the first preliminary intermediate patterns by performing an isotropic etch process on the first preliminary intermediate patterns. 
     
     
         35 . The method of  claim 33 , wherein the forming of the preliminary conductive interconnection patterns includes:
 forming a conductive material layer over the stopper layer to cover top surfaces and side surfaces of the second preliminary intermediate patterns; and   separating the conductive material layer into the preliminary conductive interconnection patterns by performing an etch-back process.   
     
     
         36 . The method of  claim 33 , wherein top surfaces of the intermediate patterns, the conductive interconnection patterns, and the filling patterns are coplanar with one another. 
     
     
         37 . The method of  claim 33 , wherein the conductive interconnection patterns include left conductive interconnection patterns formed on the left of the intermediate patterns and right conductive interconnection patterns formed on the right of the intermediate patterns,
 wherein each of the left conductive interconnection patterns includes a flat right side surface and a rounded left side surface, and   each of the right conductive interconnection patterns includes a flat left side surface and a rounded right side surface.   
     
     
         38 . The method of  claim 37 , wherein each of the intermediate patterns includes both flat side surfaces, and
 each of the filling patterns includes both side surfaces that are rounded to have negative slopes where a bottom portion is narrow and a top portion is wide.   
     
     
         39 . The method of  claim 37 , the sum of horizontal width of each left conductive interconnection pattern and horizontal width of each intermediate pattern is equal to a horizontal width of each first preliminary intermediate pattern. 
     
     
         40 . The method of  claim 37 , wherein the sum of horizontal width of each right conductive interconnection pattern and horizontal width of each intermediate pattern is equal to a horizontal width of each first preliminary intermediate pattern.