Reference generator and current source transistor based on complementary current field-effect transistor devices

Abstract

Existing proportional to absolute temperature (PTAT)/complementary-to-absolute-temperature (CTAT) reference voltage circuit requires a large components count and foot print, precise device matching for accuracy and unsatisfactory sensitivity error or variation to temperature and humidity. The present invention relates to a novel approach for such reference voltage circuit based on a self-biased complementary pair of n-type and p-type current field-effect transistors, which provides rail PTAT, rail CTAT and analog reference voltages.

What is claimed is: 
     
         1 . A proportional to absolute temperature reference voltage circuit, comprising:
 a complementary pair of a n-type current field-effect transistor (NiFET) and a p-type current field-effect transistor (PiFET), each of said NiFET and PiFET comprises:
 a source, a drain, a gate, and a diffusion, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel; 
   wherein said source of said NiFET is connected to negative power supply and said source of said PiFET is connected to positive power supply, and drains of said NiFET and said PiFET are connected together to form an output; and   wherein said gates and said output of said complimentary pair are connected together for generating a analog zero reference voltage, providing a positive rail complementary-to-absolute-temperature (or CTAT) reference voltage output at said diffusion of said PiFET and a negative rail proportional-to-absolute-temperature (or PTAT) reference voltage output at said diffusion of said NiFET.   
     
     
         2 . The proportional to absolute temperature reference voltage circuit as recited in  claim 1 , wherein said gate terminal of said PiFET and said gate of said NiFET are connected together to form a common gate. 
     
     
         3 . A positive and negative current references generator, comprising
 a. first and second complementary pairs of a n-type current field-effect transistor (NiFET) and a p-type current field-effect transistor (PiFET), each of said NiFETs and PiFETs comprises:
 a diffusion, a source, a drain and a gate, 
 defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate capacitively coupled to said source channel and said drain channel;
 wherein, for each complementary pair, said source of said NiFET is connected to negative power supply and said source of said PiFET is connected to positive power supply, and said drains of said NiFET and said PiFET are connected together to form an output; 
 
 wherein said gates of said first and second complementary pairs are connected with said output of said first complementary pair, providing a positive rail complementary-to-absolute-temperature (or CTAT) reference voltage output at said diffusion of said PiFET of said first complementary pair to said diffusion of said PiFET of said second complementary pair for generating said negative reference current; and providing a negative rail proportional-to-absolute-temperature (or PTAT) reference voltage output at said diffusion of said NiFET of said first complementary pair to said diffusion channel of said NiFET of said second complementary pair for generating said positive reference current. 
   
     
     
         4 . The positive and negative current references generator as recited in  claim 3 , wherein, for each complementary pair, said gate terminal of said PiFET and said gate of said NiFET are connected together to form a common gate. 
     
     
         5 . A stacked proportional to absolute temperature reference voltage circuit, comprising:
 a plurality of complementary pairs of a n-type current field-effect transistor (NiFET) and a p-type current field-effect transistor (PiFET), each of said NiFETs and PiFETs comprises:
 a source, a drain, a gate, and a diffusion, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate capacitively coupled to said source channel and said drain channel; 
   wherein, for each complementary pair, said drains of said NiFET and said PiFET are connected together to form an output; and   wherein, for each complementary pair, said gates are connected together with said output for generating a analog zero reference voltage, providing a positive rail complementary-to-absolute-temperature (or CTAT) reference voltage output at said diffusion of said PiFET and a negative rail proportional-to-absolute-temperature (or PTAT) reference voltage output at said diffusion of said NiFET   
       wherein said source of said NiFET of a first one of said plurality of said complementary pairs is connected to negative power supply and said source of said PiFET of said first one of said plurality of said complementary pairs is connected to positive power supply, 
       said source of said NiFET of a subsequent one of said plurality of said complementary pairs receives PTAT reference voltage output of a previous one of said plurality of said complementary pairs; said source of said PiFET of said subsequent one of said plurality of said complementary pairs receives CTAT reference voltage output of said previous one of said plurality of said complementary pairs; and said common gate of said subsequent one of said plurality of said complementary pairs receives said output of said previous one of said plurality of said complementary pairs. 
     
     
         6 . The stacked proportional to absolute temperature reference voltage circuit as recited in  claim 5 , wherein, for each complementary pair, said gate terminal of said PiFET and said gate of said NiFET are connected together to form a common gate. 
     
     
         7 . A proportional-to-absolute temperature reference voltages and complementary-to-absolute temperature reference voltages generator circuit, comprising:
 a. a first complementary pair of a n-type current field-effect transistor (NiFET) and a p-type current field-effect transistor (PiFET), and   b. a second complementary pair of NiFET and PiFET;
 each of said NiFETs and PiFETs comprises:
 a source, a drain, a gate, and a diffusion, defining a source channel between said source and said diffusion, and a drain channel between said drain and said diffusion, and said gate is capacitively coupled to said source channel and said drain channel; 
 
 wherein said drains of said NiFET and said PiFET of said first complementary pair are coupled together; 
 said drains of said NiFET and said PiFET of said second complementary pair are coupled together; 
 said source of said PiFET of said first complementary pair receives a positive power supply; 
 said source of said NiFET of said second complementary pair receives a negative power supply; 
 wherein said gates of said PiFETs of said first and said second complementary pairs and said gates of said NiFETs of said first and second complementary pairs receive said source of said NiFET of said first complementary pair and said source of said PiFET of said second complementary pair for generating a positive rail complementary-to-absolute-temperature (or CTAT) reference voltage output at said diffusion of said PiFET of said first complementary pair, CTAT analog ground reference voltage output at said diffusion of said NiFET of said first complementary pair, an analog ground reference voltage at said common gate, a negative rail proportional-to-absolute-temperature (or PTAT) reference voltage output at said diffusion of said NiFET of said second complementary pair. 
   
     
     
         8 . The proportional-to-absolute temperature reference voltages and complementary-to-absolute temperature reference voltages generator circuit as recited in  claim 7 , wherein, for each complementary pair, said gate terminal of said PiFET and said gate of said NiFET of each complementary pair are connected together to form a common gate.