Optimization of loops and data flow sections in multi-core processor environment

Abstract

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

What is claimed is: 
     
         1 . A method for operating a processor that comprises a multitude of data processing units, the method comprising:
 dividing a thread into a plurality of partitions executable on the data processing units, each partition including a plurality of instructions; and   chaining the partitions together for transferring data at least from a first partition to a second partition of the plurality of partitions,   wherein each of the partitions forms a code entity which is processed as a whole such that data is processed in each instruction of the partition after a preceding instruction of the partition without interruption.   
     
     
         2 . The method according to  claim 1 , wherein the processor is a graphics processor. 
     
     
         3 . The method according to  claim 1 , wherein the data processing units process VLIW.