Thyristor Volatile Random Access Memory and Methods of Manufacture

Abstract

A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

The invention claimed is: 
     
         1 . A method of making a volatile memory array having row lines, column lines, and an array of thyristors having anodes coupled to one of the row and column lines and having cathodes coupled to the other of the row and column lines, the method comprising:
 introducing opposite conductivity type dopant into a first conductivity type semiconductor substrate to thereby provide a buried layer providing a cathode for each of the thyristors;   forming a first conductivity type epitaxial layer on the buried layer;   removing all of the epitaxial layer and the buried layer to expose portions of the substrate from a first plurality of parallel regions extending in a first direction of the memory array to thereby form a first plurality of deep trenches;   filling the first plurality of deep trenches with insulating material;   removing all of the epitaxial layer to expose portions of the buried layer from a second plurality of parallel regions extending in a second direction of the memory array to thereby form a second plurality of shallow trenches;   filling the second plurality of shallow trenches with insulating material;   introducing opposite conductivity type dopant into an upper portion of the epitaxial layer to form upper opposite conductivity type regions separated from the buried layer by a lower portion of the epitaxial layer; and   introducing first conductivity type dopant into a top portion of the upper opposite conductivity type regions to form an anode for each of the thyristors.   
     
     
         2 . A method as in  claim 1  further comprising a step of providing an electrical connection to the anode. 
     
     
         3 . A method as in  claim 1  wherein the step of providing an electrical connection comprises:
 introducing a refractory metal into the anode; and 
 annealing the anode to thereby form a metal silicide layer. 
 
     
     
         4 . A method as in  claim 1  further comprising:
 before the step of introducing first conductivity type dopant into a top portion of the upper opposite conductivity type regions, a step of forming a further epitaxial layer on an upper surface of the epitaxial layer; and 
 later providing electrical connections to the further epitaxial layer to provide connections to the anodes of the thyristors. 
 
     
     
         5 . A method of making a volatile memory array having row lines, column lines, and an array of thyristors having anodes coupled to one of the row and column lines and having cathodes coupled to the other of the row and column lines, the method comprising:
 introducing opposite conductivity type dopant into a first conductivity type semiconductor substrate to thereby provide a buried layer providing a cathode for each of the thyristors;   forming a first epitaxial layer of first conductivity type on the buried layer;   forming a second epitaxial layer of opposite conductivity type on the first epitaxial layer;   removing all of the first and second epitaxial layers and the buried layer to expose portions of the substrate from a first plurality of parallel regions extending in a first direction of the memory array to thereby form a first plurality of deep trenches;   filling the first plurality of deep trenches with insulating material;   removing all of the of the first and second epitaxial layers to expose portions of the buried layer from a second plurality of parallel regions extending in a second direction of the memory array to thereby form a second plurality of shallow trenches;   filling the second plurality of shallow trenches with insulating material; and   introducing first conductivity type dopant into a top portion of the second epitaxial layer to form an anode for each of the thyristors.   
     
     
         6 . A method as in  claim 5  further comprising a step of providing an electrical connection to the anode. 
     
     
         7 . A method as in  claim 6  wherein the step of providing an electrical connection comprises:
 introducing a refractory metal into the anode; and 
 annealing the anode to thereby form a metal silicide layer. 
 
     
     
         8 . A method as in  claim 5  further comprising:
 before the step of introducing first conductivity type dopant into a top portion of the upper opposite conductivity type regions, a step of forming a further epitaxial layer on an upper surface of the second epitaxial layer; and 
 later providing electrical connections to the further epitaxial layer to provide connections to the anodes of the thyristors. 
 
     
     
         9 . A method as in  claim 5  wherein prior to the step of filling the first plurality of deep trenches with insulating material, steps are performed comprising:
 forming a gate insulating layer on sidewalls of the deep trenches; 
 depositing a conformal polycrystalline silicon layer in the deep trenches; and 
 removing selective portions of the conformal polycrystalline silicon layer to provide gate regions for field effect transistors. 
 
     
     
         10 . A method as in  claim 9  further comprising a step of providing electrical connections to the gate regions.