Multi-Processor System with Distributed Mailbox Architecture and Processor Error Checking Method Thereof

Abstract

A multi-processor system with a distributed mailbox architecture and a processor error checking method thereof are provided. The multi-processor system comprises a plurality of processors, each of the processors is correspondingly configured with an exclusive mailbox and an exclusive channel, and the processor error checking method comprises the following steps. When a first processor of the processors needs to communicate with a second processor, the first processor writes the data into the exclusive mailbox of the second processor through a public bus; and when the exclusive mailbox of the second processor has receiving the data, the exclusive mailbox of the second processor starts timing, and until the timing result exceeds a threshold value, the exclusive mailbox of the second processor sends a timeout signal to the second processor, and after receiving the timeout signal, the second processor resets the first processor.

What is claimed is: 
     
         1 . A multi-processor system with a distributed mailbox architecture, comprising:
 a plurality of processors, each of the processors being correspondingly configured with an exclusive mailbox and an exclusive channel;   wherein when a first processor of the processors needs to communicate with a second processor, the first processor writes data into the exclusive mailbox of the second processor through a public bus; and   when the exclusive mailbox of the second processor receives the data, the exclusive mailbox of the second processor starts timing, and until the timing result exceeds a threshold value, the exclusive mailbox of the second processor sends a timeout signal to the second processor, and after receiving the timeout signal, the second processor resets the first processor.   
     
     
         2 . The multi-processor system as claimed in  claim 1 , wherein when the first processor needs to communicate with the second processor, the first processor confirms whether the exclusive mailbox of the second processor has a sufficient storage space to store the data, if so, the first processor writes the data into the exclusive mailbox of the second processor through the public bus. 
     
     
         3 . The multi-processor system as claimed in  claim 2 , wherein each of the exclusive mailboxes is further used to output a status signal to indicate whether it has the sufficient storage space to store the data, and each of the exclusive mailboxes receives the status signals outputted from the other exclusive mailboxes. 
     
     
         4 . The multi-processor system as claimed in  claim 3 , wherein when the first processor confirms whether the exclusive mailbox of the second processor has the sufficient storage space to store the data, the first processor reads the status signal outputted by the exclusive mailbox of the second processor, and determines, according to the status signal, whether the exclusive mailbox of the second processor has the sufficient storage space to store the data. 
     
     
         5 . The multi-processor system as claimed in  claim 4 , wherein when the exclusive mailbox of the second processor has receiving the data, the exclusive mailbox of the second processor stops and resets the timing to zero, and sends an interrupt signal to the second processor, and after receiving the interrupt signal, the second processor reads the data in the exclusive mailbox through the exclusive channel. 
     
     
         6 . The multi-processor system as claimed in  claim 5 , wherein each of the exclusive mailboxes further comprises:
 a control register for setting an interrupt condition of the exclusive mailbox; and   a mailbox controller for managing the storage space as well as generating the timeout signal, the interrupt signal and the status signal.   
     
     
         7 . A processor error checking method for executing in a multi-processor system, the multi-processor system comprising a plurality of processors, each of the processors being correspondingly configured with an exclusive mailbox and an exclusive channel, and the processor error checking method comprising the following steps of:
 when a first processor of the processors needing to communicate with a second processor, the first processor writing data into the exclusive mailbox of the second processor through a public bus; and   when the exclusive mailbox of the second processor receiving the data, the exclusive mailbox of the second processor starting timing, and until the timing result exceeding a threshold value, the exclusive mailbox of the second processor sending a timeout signal to the second processor, and after receiving the timeout signal, the second processor resetting the first processor.   
     
     
         8 . The processor error checking method as claimed in  claim 7 , wherein when the first processor needs to communicate with the second processor, the first processor confirms whether the exclusive mailbox of the second processor has a sufficient storage space to store the data, if so, the first processor writes the data into the exclusive mailbox of the second processor through the public bus. 
     
     
         9 . The processor error checking method as claimed in  claim 8 , wherein each of the exclusive mailboxes is further used to output a status signal to indicate whether it has the sufficient storage space to store the data, and each of the exclusive mailboxes receives the status signals outputted from the other exclusive mailboxes. 
     
     
         10 . The processor error checking method as claimed in  claim 9 , wherein when the first processor confirms whether the exclusive mailbox of the second processor has the sufficient storage space to store the data, the first processor reads the status signal outputted by the exclusive mailbox of the second processor, and determines, according to the status signal, whether the exclusive mailbox of the second processor has the sufficient storage space to store the data. 
     
     
         11 . The processor error checking method as claimed in  claim 10 , wherein when the exclusive mailbox of the second processor has receiving the data, the exclusive mailbox of the second processor stops and resets the timing to zero, and sends an interrupt signal to the second processor, and after receiving the interrupt signal, the second processor reads the data in the exclusive mailbox through the exclusive channel. 
     
     
         12 . The processor error checking method as claimed in  claim 11 , wherein each of the exclusive mailboxes further comprises:
 a control register for setting an interrupt condition of the exclusive mailbox; and   a mailbox controller for managing the storage space as well as generating the timeout signal, the interrupt signal and the status signal.