Network-enabled graphics processing module

Abstract

A system disclosed within this document is capable of improving performance in virtual computing environments, e.g., by reducing latency associated with streaming video data between a client device and an associated server system over a network. As discussed in detail below, such performance improvements can be achieved using techniques that avoid, reduce and/or overlap operations that are executed by the server system in order to render, encode, and/or transmit video data to a client device over a network. Such techniques can be used to reduce propagation and/or processing delays imposed by, for example, the server system's CPU operations, input/output (I/O), infrastructure, NIC, OS processes, among other types of hardware and software-based overheads. In various implementations, the performance enhancements can be realized at the rendering, encoding, or transmission operations performed by the server system.

What is claimed is: 
     
         1 . A system comprising:
 one or more central processing units;   a graphics processing unit comprising a first memory and configured to exchange data communications with the one or more central processing units without accessing resources of the one or more central processing units;   a network interface controller comprising a second memory; and   a non-transitory computer-readable storage device storing instructions that, when executed by the one or more central processing units, cause the graphics processing unit to perform operations comprising:
 encoding, within the first memory, one or more frames of video data to generate encoded video data; 
 buffering, within the first memory, the encoded video data without accessing the second memory; and 
 providing, to the network interface controller, an instruction to provide a portion of the encoded video data for output while the encoded video data is being buffered within the first memory. 
   
     
     
         2 . The system of  claim 1 , wherein encoding the one or more frames of video data to generate the encoded video data comprises:
 encoding a first portion of the video data;   encoding a second portion of the video data that is different from the first portion of the video data; and   storing the encoded first portion in the second memory while encoding the second portion of the video data.   
     
     
         3 . The system of  claim 1 , wherein the graphics processing unit and the one or more central processing units are housed on a graphics chip. 
     
     
         4 . The system of  claim 3 , wherein the graphics processing unit and the one or more central processing units share caching and physical memory spaces on the graphics chip. 
     
     
         5 . The system of  claim 1 , wherein the one or more central processing units are configured to exchange direct communications with the graphics processing unit. 
     
     
         6 . The system of  claim 1 , wherein the graphics processing unit is configured to use a peripheral interconnect that permits data communication between the graphics processing unit and the one or more central processing units without accessing resources of the one or more central processing units. 
     
     
         7 . The system of  claim 1 , wherein the instructions stored by the non-transitory computer-readable storage device causes the graphics processing unit to further perform operations comprising:
 encapsulating, within the first memory, the one or more frames of video data to generate encapsulated video data that includes one or more network protocol headers of the network interface controller; and   wherein encoding the one or more frames of video data to generate the encoded video data comprises encoding one or more frames of the encapsulated video data.   
     
     
         8 . A method comprising:
 encoding, by a graphics processing unit and within a first memory of the graphics processing unit, one or more frames of video data to generate encoded video data, wherein the graphics processing unit is configured to exchange data communications with one or more central processing units without accessing resources of the one or more central processing units;   buffering, by the graphics processing unit and within the first memory, the encoded video data without accessing a second memory of a network interface controller; and   providing, to the network interface controller, an instruction to provide a portion of the encoded video data for output while the encoded video data is being buffered within the first memory.   
     
     
         9 . The method of  claim 8 , wherein encoding the one or more frames of video data to generate the encoded video data comprises:
 encoding a first portion of the video data;   encoding a second portion of the video data that is different from the first portion of the video data; and   storing the encoded first portion in the second memory while encoding the second portion of the video data.   
     
     
         10 . The method of  claim 8 , wherein the graphics processing unit and the one or more central processing units are housed on a graphics chip. 
     
     
         11 . The method of  claim 10 , wherein the graphics processing unit and the one or more central processing units share caching and physical memory spaces on the graphics chip. 
     
     
         12 . The method of  claim 8 , wherein the one or more central processing units are configured to exchange direct communications with the graphics processing unit. 
     
     
         13 . The method of  claim 8 , wherein the graphics processing unit is configured to use a peripheral interconnect that permits data communication between the graphics processing unit and the one or more central processing units without accessing resources of the one or more central processing units. 
     
     
         14 . The method of  claim 8 , further comprising:
 encapsulating, within the first memory, the one or more frames of video data to generate encapsulated video data that includes one or more network protocol headers of the network interface controller; and   wherein encoding the one or more frames of video data to generate the encoded video data comprises encoding one or more frames of the encapsulated video data.   
     
     
         15 . A non-transitory computer-readable storage device storing instructions associated with one or more central processing units and a graphics processing unit and storing instructions that, when executed by one or more central processing units, cause the graphics processing unit to perform operations comprising:
 encoding, by the graphics processing unit and within a first memory of the graphics processing unit, one or more frames of video data to generate encoded video data, wherein the graphics processing unit is configured to exchange data communications with one or more central processing units without accessing resources of the one or more central processing units;   buffering, by the graphics processing unit and within the first memory, the encoded video data without accessing a second memory of a network interface controller; and   providing, to the network interface controller, an instruction to provide a portion of the encoded video data for output while the encoded video data is being buffered within the first memory.   
     
     
         16 . The storage device of  claim 15 , wherein encoding the one or more frames of video data to generate the encoded video data comprises:
 encoding a first portion of the video data;   encoding a second portion of the video data that is different from the first portion of the video data; and   storing the encoded first portion in the second memory while encoding the second portion of the video data.   
     
     
         17 . The storage device of  claim 16 , wherein the graphics processing unit and the one or more central processing units are housed on a graphics chip. 
     
     
         18 . The storage device of  claim 17 , wherein the graphics processing unit and the one or more central processing units share caching and physical memory spaces on the graphics chip. 
     
     
         19 . The storage device of  claim 15 , wherein the one or more central processing units are configured to exchange direct communications with the graphics processing unit. 
     
     
         20 . The storage device of  claim 15 , wherein the graphics processing unit is configured to use a peripheral interconnect that permits data communication between the graphics processing unit and the one or more central processing units without accessing resources of the one or more central processing units.