Memory having different reliabilities

Abstract

The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.

1 . A circuit, comprising:
 a memory which comprises a multiplicity of memory cells,   wherein the memory comprises a first area and a second area,   wherein at least one memory cell of the multiplicity of memory cells comprises a part of the first area and a part of the second area,   wherein the first area has a lower reliability than the second area,   wherein the circuit is configured such that first bits are stored in the first area and second bits are stored in the second area.   
     
     
         2 . The circuit as claimed in  claim 1 , wherein the memory cells assume physical values on the basis of the digital values stored therein, frequency distributions of the physical values which correspond to different digital values in the second area having a smaller overlap than frequency distributions which correspond to different digital values in the first area. 
     
     
         3 . The circuit as claimed in  claim 1 , wherein more than two values are stored for each memory cell. 
     
     
         4 . The circuit as claimed in  claim 1 , wherein the memory is a non-volatile memory. 
     
     
         5 . The circuit as claimed in  claim 1 , wherein a second bit exists for at least one first bit, which second bit is stored in the same memory cell. 
     
     
         6 . The circuit as claimed in  claim 5 , wherein a second bit exists for each first bit, which second bit can be stored in the same memory cell. 
     
     
         7 . The circuit as claimed in  claim 5 , wherein the first bits and the second bits are different. 
     
     
         8 . The circuit as claimed in  claim 1 , wherein, in the error-free case, one of the first bits stored in the memory and/or one of the second bits stored in the memory is/are a bit of a code word of an error code. 
     
     
         9 . The circuit as claimed in  claim 8 , wherein, in the error-free case, a code word of the error code is determined on the basis of the first bits stored in the memory, address bits and/or bits derived from address bits. 
     
     
         10 . The circuit as claimed in  claim 1 , wherein, in the error-free case, one of the first bits stored in the memory is a bit of a code word of a first error code. 
     
     
         11 . The circuit as claimed in  claim 1 , wherein, in the error-free case, one of the second bits stored in the memory is a bit of a code word of a second error code. 
     
     
         12 . The circuit as claimed in  claim 10 , wherein the first error code and the second error code are different or identical error codes. 
     
     
         13 . The circuit as claimed in  claim 10 , wherein the first error code has a higher correction power than the second error code. 
     
     
         14 . The circuit as claimed in  claim 10 , which is set up in such a manner that first bits corrected using the first error code are provided from the first area when reading the memory. 
     
     
         15 . The circuit as claimed in  claim 14 , comprising a further memory, the circuit configured such that the corrected first bits are stored in the further memory. 
     
     
         16 . The circuit as claimed in  claim 15 , the circuit configured such that the corrected first bits are coded using a further error code and are stored in the further memory. 
     
     
         17 . The circuit as claimed in  claim 16 , wherein, in the error-free case, a code word of the further error code can be determined on the basis of the bits stored in the further memory, address bits and/or bits derived from address bits. 
     
     
         18 . The circuit as claimed in  claim 1 , wherein the further memory is a volatile or non-volatile memory. 
     
     
         19 . The circuit as claimed in  claim 1 , which is set up such that:
 the memory cell of the memory is written to or read using at least three reference values R l , R m , R r , where R l <R m <R r ,   a value z being stored in the memory cell,   the value of one bit of the second bits being determined by comparing the value z with the reference value R m , and   the value of one bit of the first bits being determined by comparing the value z with the reference value R m  and with at least one further reference value which differs from the reference value R m .   
     
     
         20 . The circuit as claimed in  claim 19 , wherein the memory cell is written to in such a manner that the following applies to the value z in the error-free case:
   | R   l   −z|<|R   m   −z | for  z<R   m  and     | R   r   −z|<|R   m   −z | for  z>R   m .