System and method for performing a concurrent multiple page read of a memory array

Abstract

A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

1 . (canceled) 
     
     
         2 . A circuit comprising:
 first wordline control logic including first driver circuitry to apply a first voltage to a first wordline to access a first plane; and   second wordline control logic including second driver circuitry to apply a second voltage to a second wordline to access a second plane concurrently with the application of the first voltage to the first wordline to access the first plane.   
     
     
         3 . The circuit of  claim 2 , wherein:
 the first wordline control logic includes a first voltage regulator to generate the first voltage; and   wherein the second wordline control logic includes a second voltage regulator to generate the second voltage.   
     
     
         4 . The circuit of  claim 2 , wherein:
 the first voltage is for selection of memory cells at a first programming level and the second voltage is for selection of second memory cells at a second programming level.   
     
     
         5 . The circuit of  claim 4 , wherein:
 the first programming level and the second programming level comprise different levels for MLC, TLC, or QLC NAND memory cells.   
     
     
         6 . The circuit of  claim 2 , wherein the first voltage is independent of the second voltage. 
     
     
         7 . The circuit of  claim 2 , wherein the first wordline control logic and the second wordline control logic are comprised in CMOS under a memory array comprising the first and second planes. 
     
     
         8 . A memory device comprising:
 a memory array comprising a first plane and a second plane; and   control circuitry comprising:
 first wordline control logic including first driver circuitry to apply a first voltage to a first wordline to access the first plane, and 
 second wordline control logic including second driver circuitry to apply a second voltage to a second wordline to access the second plane concurrently with the application of the first voltage to the first wordline to access the first plane. 
   
     
     
         9 . The memory device of  claim 8 , wherein:
 the first wordline control logic includes a first voltage regulator to generate the first voltage; and wherein the second wordline control logic includes a second voltage regulator to generate the second voltage.   
     
     
         10 . The memory device of  claim 8 , wherein:
 the first voltage is for selection of memory cells at a first programming level and the second voltage is for selection of second memory cells at a second programming level.   
     
     
         11 . The memory device of  claim 10 , wherein:
 the first programming level and the second programming level comprise different levels of MLC, TLC, or QLC NAND memory cells.   
     
     
         12 . The memory device of  claim 8 , wherein the first voltage is independent of the second voltage. 
     
     
         13 . The memory device of  claim 8 , wherein the first wordline control logic and the second wordline control logic are comprised in CMOS under the memory array. 
     
     
         14 . The memory device of  claim 8 , wherein the memory array comprises a three-dimensional (3D) NAND memory array. 
     
     
         15 . A system comprising:
 a processor; and   memory coupled with the processor, the memory comprising:
 a memory array comprising a first plane and a second plane; and 
 control circuitry comprising:
 first wordline control logic including first driver circuitry to apply a first voltage to a first wordline to access the first plane, and 
 second wordline control logic including second driver circuitry to apply a second voltage to a second wordline to access the second plane concurrently with the application of the first voltage to the first wordline to access the first plane. 
 
   
     
     
         16 . The system of  claim 15 , wherein:
 the first wordline control logic includes a first voltage regulator to generate the first voltage; and   wherein the second wordline control logic includes a second voltage regulator to generate the second voltage.   
     
     
         17 . The system of  claim 15 , wherein:
 the first voltage is for selection of memory cells at a first programming level and the second voltage is for selection of second memory cells at a second programming level.   
     
     
         18 . The system of  claim 17 , wherein:
 the first programming level and the second programming level comprise different levels of MLC, TLC, or QLC NAND memory cells.   
     
     
         19 . The system of  claim 15 , wherein the first wordline control logic and the second wordline control logic are comprised on a same chip as the memory array. 
     
     
         20 . The system of  claim 19 , wherein the first wordline control logic and the second wordline control logic are comprised in CMOS under the memory array. 
     
     
         21 . The system of  claim 15 , wherein the memory array comprises a three-dimensional (3D) NAND memory array. 
     
     
         22 . The system of  claim 15 , wherein the memory is comprised in a solid state drive (SSD).