Methods and apparatus for reducing microbumps for inter-die double-data rate (ddr) transfer

Abstract

An inter-die double data rate (DDR) data transfer scheme is provided. In particular, the data transfer scheme utilizes an error correction code (ECC) encoding scheme that exploits the DDR property that a single microbump defect can only yield four possible error scenarios. A specialized single error correcting, double error detecting, and double adjacent error correcting (SEC-DED-DAEC) encoding scheme that imposes at least four parity check matrix constraints may be used. Configured and operated in this way, a fewer number of parity check bits are required to detect data bit errors associated with a single defective microbump.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a first group of bumps configured to receive data bits from another integrated circuit;   a second group of bumps configured to receive parity bits from the another integrated circuit, wherein the data bits and the parity bits are transmitted to the another integrated circuit using a double data rate (DDR) transfer scheme; and   a syndrome bit generating circuit that is configured to receive the data bits from the first group of bumps and that is configured to implement a decoding scheme that exploits an error characteristic associated with the DDR transfer scheme at a defective bump in the first group of bumps to reduce the total number of required bumps in the second group of bumps.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the defective bump is configured to receive an even data bit at a rising clock edge and an odd data bit at a falling clock edge. 
     
     
         3 . The integrated circuit of  claim 2 , wherein the error characteristic associated with the DDR transfer scheme at the defective bump comprises up to four possible error scenarios. 
     
     
         4 . The integrated circuit of  claim 3 , wherein the four possible error scenarios comprise a single error at the even data bit and a single error at the odd data bit. 
     
     
         5 . The integrated circuit of  claim 4 , wherein the four possible error scenarios further comprises errors at both the even data bit and the odd data bit and no errors at the even data bit and the odd data bit. 
     
     
         6 . The integrated circuit of  claim 1 , wherein the decoding scheme of the syndrome bit generating circuit is implemented based on a single error correcting, double error detecting, and double adjacent error correcting (SEC-DED-DAEC) error correcting code (ECC) scheme. 
     
     
         7 . The integrated circuit of  claim 6 , wherein the SEC-DED-DAEC ECC scheme imposes at least four constraints on a parity check matrix that determines the configuration of the syndrome bit generating circuit. 
     
     
         8 . The integrated circuit of  claim 7 , wherein the at least four constraints stipulates that:
 a) no columns in the parity check matrix are all zeros;   b) every column in the parity check matrix is distinct; and   c) every column in the parity check matrix contains an odd number of ones.   
     
     
         9 . The integrated circuit of  claim 8 , wherein the at least four constraints further stipulates that:
 d) every even and odd column pair in the parity check matrix is distinct.   
     
     
         10 . The integrated circuit of  claim 9 , wherein the syndrome bit generating circuit is implemented based on values in the parity check matrix and also based on additional parity bits obtained by combining even and odd columns in the parity check matrix. 
     
     
         11 . The integrated circuit of  claim 10 , wherein the additional parity bits allow the syndrome bit generating circuit to identify adjacent even and odd bit errors at the defective bump. 
     
     
         12 . An integrated circuit, comprising:
 a first group of bumps configured to output data bits to another integrated circuit;   a second group of bumps configured to output parity bits to the another integrated circuit; and   a parity bit generating circuit that is configured to receive the data bits and that is configured to implement an encoding scheme that reduces the total number of required bumps in the second group of bumps by taking advantage of a double data rate (DDR) error characteristic of a defective bump in the first group of bumps.   
     
     
         13 . The integrated circuit of  claim 12 , wherein the defective bump is configured to receive an even data bit at a rising clock edge and an odd data bit at a falling clock edge. 
     
     
         14 . The integrated circuit of  claim 13 , wherein the DDR error characteristic associated with the DDR transfer scheme at the defective bump comprises four possible error scenarios. 
     
     
         15 . The integrated circuit of  claim 14 , wherein the four possible error scenarios comprise:
 a single error at the even data bit;   a single error at the odd data bit;   a double error at both the even data bit and the odd data bit; and   no errors at the even data bit and the odd data bit.   
     
     
         16 . The integrated circuit of  claim 12 , wherein the encoding scheme of the parity bit generating circuit is implemented based on a single error correcting, double error detecting, and double adjacent error correcting (SEC-DED-DAEC) error correcting code (ECC) scheme. 
     
     
         17 . A system, comprising:
 a first integrated circuit die; and   a second integrated circuit die configured to communicate with the first integrated circuit die via a plurality of microbumps, wherein:
 the first integrated circuit die is configured to transmit data bits to the second integrated circuit die using a double data rate (DDR) toggling scheme; and 
 the first integrated circuit die comprises an encoder circuit configured to encode the data bits using an error correcting code (ECC) scheme that is capable of detecting and correcting adjacent even and odd data bit errors at a defective microbump in the plurality of microbumps. 
   
     
     
         18 . The system of  claim 17 , wherein the ECC scheme comprises a single error correcting, double error detecting, and double adjacent error correcting (SEC-DED-DAEC) scheme that requires fewer parity bits than a single error correcting and double error detecting (SEC-DED) scheme. 
     
     
         19 . The system of  claim 18 , wherein the SEC-DED-DAEC scheme imposes at least the following constraints on an H-matrix that determines the configuration of the encoder circuit:
 a) no columns in the H-matrix are all zeros;   b) every column in the H-matrix is distinct;   c) every column in the H-matrix contains an odd number of ones; and   d) a function of an even column and an odd column in each associated column pair is distinct from the function of an even column and an odd column of every other column pair in the H-matrix.   
     
     
         20 . The system of  claim 19 , wherein the second integrated circuit die comprises a decoder circuit configured to decode the data bits received from the first integrated circuit, and wherein the decoder circuit is implemented based on the H-matrix and also based on additional parity bits generated by taking the function of the even column and the odd column in each column pair of the H-matrix.