Phase demodulation method and circuit

Abstract

An electrical circuit and method for de-modulation and carrier recovery of PSK modulated carrier signals in analog domain are described. A portion of the received PSK-modulated carrier signal is passed through a signal multiplication circuit to obtain a frequency-multiplied carrier that is absent of the PSK modulation, which is then passed through a frequency dividing circuit to obtain a reference carrier at the received carrier frequency. The reference signal is then mixed with the received PSK-modulated carrier signal to obtain a de-modulated baseband signal. The method may be used in heterodyne receivers of optical BPSK and QPSK signals.

What is claimed is: 
     
         1 . An electrical circuit for demodulating a received phase shift keying (PSK) signal, the electrical circuit comprising:
 a first signal splitter configured to split the received PSK signal to obtain a first PSK signal and a second PSK signal, wherein each of the first PSK signal and the second PSK signal comprises a PSK-modulated carrier wave with a carrier wave frequency f;   a multiplying circuit configured to convert the first PSK signal into a frequency-multiplied carrier signal absent of PSK modulation;   a frequency dividing circuit configured to obtain, from the frequency multiplied carrier signal, a first reference carrier wave signal at the carrier wave frequency f; and,   a first electrical signal mixer configured to mix the first reference carrier wave signal with the second PSK signal to obtain a first de-modulated signal.   
     
     
         2 . The electrical circuit of  claim 1 , wherein the frequency dividing circuit comprises a switching circuit. 
     
     
         3 . The electrical circuit of  claim 2 , wherein the switching circuit is configured to block every other oscillation of the frequency-multiplied carrier signal. 
     
     
         4 . The electrical circuit of  claim 2 , wherein the switching circuit is configured to be triggered by one of a rising edge or a falling edge of the frequency-multiplied carrier signal for frequency down-conversion without frequency or phase locking. 
     
     
         5 . The electrical circuit of  claim 2 , wherein the multiplying circuit comprises at least one electrical signal mixer. 
     
     
         6 . The electrical circuit of  claim 4  comprising an edge-sharpening filter disposed upstream of the switching circuit. 
     
     
         7 . The electrical circuit of  claim 6  comprising a low-pass filter disposed downstream of the switching circuit, the low-pass filter having a passband including the carrier wave frequency f but excluding harmonics thereof. 
     
     
         8 . The electrical circuit of  claim 1 , wherein the multiplying circuit comprises a signal squaring circuit. 
     
     
         9 . The electrical circuit of  claim 1  wherein the frequency dividing circuit is configured to obtain a second reference carrier wave signal that is phase-shifted relative to the first reference carrier wave signal; comprising a second electrical signal mixer configured to mix the second reference carrier wave signal with the second PSK signal to extract a second de-modulated signal from the second PSK signal. 
     
     
         10 . The electrical circuit of  claim 9  wherein the second reference carrier wave signal is phase-shifted relative to the first reference carrier wave signal by 90°. 
     
     
         11 . The electrical circuit of  claim 9  comprising a signal combining circuit disposed to combine the first and second de-modulated signals. 
     
     
         12 . The electrical circuit of  claim 9  wherein the received PSK signal comprises a quadrature PSK (QPSK) signal, and wherein the multiplying circuit comprises two signal squaring circuits connected in series. 
     
     
         13 . The electrical circuit of  claim 12  wherein the frequency diving circuit comprises a first frequency divider disposed downstream of the multiplying circuit, and a second signal splitter disposed downstream of the multiplying circuit. 
     
     
         14 . The electrical circuit of  claim 13  wherein the second signal splitter is disposed downstream of the first frequency divider. 
     
     
         15 . The electrical circuit of  claim 14  comprising a second frequency divider coupled to the second signal splitter to obtain the first reference carrier wave signal, and a third frequency divider coupled to the second signal splitter to obtain the second reference carrier wave signal. 
     
     
         16 . The electrical circuit of  claim 15  wherein the second frequency divider and the third frequency divider comprise switching circuits configured to be triggered by different edges of input signals thereof. 
     
     
         17 . The electrical circuit of  claim 13  wherein the first frequency divider comprises a switching circuit configured to be triggered by one of a rising edge or falling edge of an input signal thereof, comprising an edge sharpening filter disposed upstream of the first frequency divider.