Voltage regulator circuit with high power supply rejection ratio

Abstract

An amplifier circuit generates a control signal as a function of a difference between a reference signal and a feedback signal. The control signal is filtered by a low pass filter circuit to generate a filtered control signal. The control signal is applied to the control terminal of a first ballast transistor which sources current to an output node. The filtered control signal is applied to the control terminal of a second ballast transistor which also sources current to the output node. In response to the sourced currents, an output voltage is generated at the output node. A feedback circuit coupled to the output node generates the feedback signal.

What is claimed is: 
     
         1 . A circuit, comprising:
 an amplifier circuit configured to generate a control signal as a function of a difference between a reference signal and a feedback signal;   a filter circuit configured to filter the control signal and generate a filtered control signal;   a ballast circuit comprising:
 a first ballast transistor coupled to source current to an output node and having a gate terminal that is directly driven by the control signal; and 
 a second ballast transistor coupled to source current to the output node and having a gate terminal that is directly driven by the filtered control signal; and 
   a feedback circuit coupled to the output node and configured to generate the feedback signal.   
     
     
         2 . The circuit of  claim 1 , wherein said first and second ballast transistors are connected in parallel between a supply voltage node and the output node. 
     
     
         3 . The circuit of  claim 1 , wherein the filter circuit is a low pass filter circuit. 
     
     
         4 . The circuit of  claim 1 , wherein the feedback circuit is a resistive voltage divider circuit. 
     
     
         5 . The circuit of  claim 1 , wherein the first and second ballast transistors are p-channel MOSFETs. 
     
     
         6 . The circuit of  claim 5 , wherein:
 the first ballast transistor has a source terminal directly connected to a power supply node and a drain terminal directly connected to the output node; and   the second ballast transistor has a source terminal directly connected to the power supply node and a drain terminal directly connected to the output node.   
     
     
         7 . The circuit of  claim 1 , further comprising a switching circuit connected in parallel with the filter circuit and configured, when actuated, to bypass the filter circuit and directly drive the gate terminal of the second ballast transistor with the control signal. 
     
     
         8 . The circuit of  claim 7 , further comprising a control circuit configured to control actuation of the switching circuit. 
     
     
         9 . The circuit of  claim 8 , wherein the control circuit actuates the switching circuit during circuit start-up. 
     
     
         10 . The circuit of  claim 8 , wherein the control circuit is configured to sense load current at the output node and selectively deactuate the switching circuit in response to sensing the load current. 
     
     
         11 . A method, comprising:
 determining a difference between a reference signal and a feedback signal;   generating a control signal in response to said difference;   filtering the control signal to generate a filtered control signal;   modulating a conductivity of a first ballast transistor in response to the control signal to generate a first current;   modulating a conductivity of a second ballast transistor in response to the filtered control signal to generate a second current;   applying the first and second currents to an output node to generate an output voltage; and   generating the feedback signal from the output voltage.   
     
     
         12 . The method of  claim 11 , wherein filtering comprises low pass filtering. 
     
     
         13 . The method of  claim 11 , wherein generating comprises dividing the output voltage. 
     
     
         14 . The method of  claim 11 , further comprising selectively bypassing the filtering so as to modulate the conductivity of the second ballast transistor in response to the control signal. 
     
     
         15 . The method of  claim 14 , wherein bypassing occurs during circuit start-up. 
     
     
         16 . The method of  claim 14 , further comprising:
 sensing load current at the output node; and   selectively deactuating bypassing in response to the senses load current.   
     
     
         17 . A method, comprising:
 selecting a size of a ballast transistor for a low drop out (LDO) voltage regulator application, said size comprising a transistor width W and a transistor length L;   splitting the ballast transistor into a first ballast transistor and a second ballast transistor by a factor M, wherein the first ballast transistor has a size comprising a transistor width W/M and a length L and wherein the second ballast transistor has a size comprising a transistor width of W(1-1/M) and a length L; and   selecting a frequency response of a filter circuit for filtering a control signal to be applied to the control terminal of the first ballast transistor in order to generate a filtered control signal to be applied to the control terminal of the second ballast transistor.   
     
     
         18 . The method of  claim 17 , further comprising:
 selecting an output stage capacitance for the LDO voltage regulator application; and   dividing the compensation capacitance by M to choose an output stage capacitor to be coupled to an output of the voltage regulator.   
     
     
         19 . The method of  claim 17 , further comprising:
 selecting a bias current level of an error amplifier for the LDO voltage regulator application; and   dividing the bias current level by M to specify error amplifier bias current for the error amplifier generating said control signal.