Physical partitioning of computing resources for server virtualization

Abstract

A baseboard management controller (BMC) can physically partition the computing resources of a physical host into different resource groups for concurrently running a different operating system per resource group. The BMC can allocate a first processor of the host to a first resource group and a second processor of the host to a second resource group. The BMC can separate the memory of the host into a first memory range for the first processor and a second memory range for the second processor, and the BMC can limit access to the first memory range to the first processor and limit access to the second memory range to the second processor. The BMC can also distribute physical or virtual peripheral devices of the host between the first processor and the second processor.

What is claimed is: 
     
         1 . A computer-implemented method comprising:
 partitioning a portion of a memory for exclusive use by one of a plurality of processors;   mapping a peripheral device to the portion of the memory to provide access to the one of the plurality of processors; and   executing an operating system via the portion of the memory.   
     
     
         2 . The computer-implemented method of  claim 1 , wherein one or more memory controllers are configured to control the portion of the memory. 
     
     
         3 . The computer-implemented method of  claim 2 , further comprising:
 configuring one or more other memory controllers to deny the access of the one of the plurality of processors to other ranges of memory, the one or more other memory controllers not having control over the portion of the memory.   
     
     
         4 . The computer-implemented method of  claim 1 , further comprising:
 generating a memory map that maps the portion of the memory to a first set of dual inline memory modules (DIMMs) of a physical host and that excludes mappings to other DIMMs of the physical host.   
     
     
         5 . The computer-implemented method of  claim 1 , further comprising:
 disabling cache coherency between the portion of the memory and another portion of the memory.   
     
     
         6 . The computer-implemented method of  claim 1 , further comprising:
 receiving at least a first boot image including first instructions for loading a first operating system and a second boot image including second instructions for loading a second operating system;   loading the first boot image into the portion of the memory and the second boot image into another portion of the memory;   executing the first instructions for loading the first operating system; and   executing the second instructions for loading the second operating system.   
     
     
         7 . The computer-implemented method of  claim 1 , further comprising:
 providing access to the one of the plurality of processors to an input/output (I/O) port by exposing the I/O port to the one of the plurality of processors.   
     
     
         8 . The computer-implemented method of  claim 1 , further comprising:
 denying access to the one of the plurality of processors to an I/O port by hiding the I/O port from the one of the plurality of processors.   
     
     
         9 . The computer-implemented method of  claim 1 , further comprising:
 mapping memory of a peripheral device to the portion of the memory to provide access to the one of the plurality of processors to the peripheral device.   
     
     
         10 . The computer-implemented method of  claim 1 , further comprising:
 denying access to a peripheral device by excluding a mapping of memory of the peripheral device to the portion of the memory.   
     
     
         11 . The computer-implemented method of  claim 1 , further comprising:
 sending, by the one of the plurality of processors, an I/O request to a peripheral device connected to a physical host; and   receiving, by the one of the plurality of processors, an I/O response from the peripheral device.   
     
     
         12 . The computer-implemented method of  claim 1 , further comprising:
 sending, the one of the plurality of processors, an I/O request to a peripheral device connected to a physical host; and   ignoring, by the peripheral device, the I/O request.   
     
     
         13 . A server comprising:
 a processor; and   a memory including instructions that, upon execution by the processor, cause the processor to:
 partition a portion of a memory for exclusive use by one of a plurality of processors; 
 map a peripheral device to the portion of the memory to provide access to the one of the plurality of processors; and
 execute an operating system via the portion of the memory. 
 
   
     
     
         14 . The server of  claim 13 ,
 wherein,
 the one of the plurality of processors include a first central processing unit (CPU), and 
 one or more other processors of the plurality of processors include a second CPU. 
   
     
     
         15 . The server of  claim 13 ,
 wherein,
 the one of the plurality of processors include a first core of a multi-core processor, and 
 one or more other processors of the plurality of processors include a second core of the multi-core processor. 
   
     
     
         16 . The server of  claim 13 ,
 wherein,
 the one of the plurality of processors include a first core of a first multi-core processor, and 
 one or more other processors of the plurality of processors include a second core of a second multi-core processor. 
   
     
     
         17 . A non-transitory computer-readable medium having instructions that, upon execution by a processor, cause the processor to:
 partition a portion of a memory for exclusive use by one of a plurality of processors;   map a peripheral device to the portion of the memory to provide access to the one of the plurality of processors; and   execute an operating system via the portion of the memory.   
     
     
         18 . The non-transitory computer-readable medium of  claim 17 , wherein the instructions upon execution further cause the processor to:
 virtualize a physical memory controller to create a first virtual memory controller and a second virtual memory controller;   allocate the first virtual memory controller to a first resource group; and   allocate the second virtual memory controller to a second resource group.   
     
     
         19 . The non-transitory computer-readable medium of  claim 17 , wherein the instructions further cause the processor to:
 virtualize a physical peripheral device using Single Root I/O Virtualization to create at least a first virtual peripheral device and a second virtual peripheral device;   allocate the first virtual peripheral device to a first resource group; and   allocate the second virtual peripheral device to a second resource group.   
     
     
         20 . The non-transitory computer-readable medium of  claim 17 , wherein the instructions further cause the processor to:
 virtualize a physical peripheral device using Multi I/O Virtualization to create at least a first virtual peripheral device and a second virtual peripheral device;   allocate the first virtual peripheral device to a first resource group; and   allocate the second virtual peripheral device to a second resource group.