US2020142854A1PendingUtilityA1

Multilane heterogeneous serial bus

Assignee: QUALCOMM INCPriority: Feb 28, 2018Filed: Jan 8, 2020Published: May 7, 2020
Est. expiryFeb 28, 2038(~11.6 yrs left)· nominal 20-yr term from priority
G06F 2213/0016G06F 13/4291
59
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Claims

Abstract

Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes configuring a first interface to exchange data over two primary wires of a serial bus in accordance with a first I3C protocol, and configuring a second interface to communicate over at least one secondary wire in accordance with a second I3C protocol. In one example, the first data is encoded in a sequence of symbols representing signaling state of the two primary wires. A recovered clock signal may be derived from transitions between symbol transmission intervals in the first interface may be used to control double data rate communication through the second interface.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus adapted for data communication, comprising:
 a plurality of line interface circuits configured to couple the apparatus to a plurality of wires; and   a controller configured to:
 configure the plurality of line interface circuits to provide a first group of wires in the plurality of wires for exchanging data when the apparatus is conducting a transaction with another device, wherein the first group of wires includes at least three wires; 
 configure a frame duration for the transaction; and 
 configure a number of bits of the data to be transmitted in each frame of the transaction. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the frame duration is defined by a number of cycles of a clock signal used to control timing of data transmissions during the transaction. 
     
     
         3 . The apparatus of  claim 1 , wherein the number of bits of the data is a multiple of a number of cycles of a clock signal used to control timing of the transaction. 
     
     
         4 . The apparatus of  claim 1 , further comprising:
 a symbol encoder configured to encode data in one or more sets of symbols transmitted over the first group of wires during the transaction, wherein each of the first group of wires carries one bit of a symbol in each symbol transmission interval provided in the transaction.   
     
     
         5 . The apparatus of  claim 4 , wherein each set of symbols is transmitted in five symbol transmission intervals. 
     
     
         6 . The apparatus of  claim 4 , wherein the controller is further configured to:
 configure the symbol encoder for a symbol encoding mode that uses the first group of wires to transmit each symbol.   
     
     
         7 . The apparatus of  claim 6 , wherein the number of bits of the data to be transmitted in each frame of the transaction is determined by encoding efficiency of the symbol encoding mode. 
     
     
         8 . The apparatus of  claim 1 , wherein the controller is further configured to:
 configure the plurality of line interface circuits to provide a second group of wires in the plurality of wires for transmitting or receiving additional data during the transaction.   
     
     
         9 . The apparatus of  claim 8 , wherein the controller is further configured to:
 transmit or receive the additional data in accordance with a single data rate protocol.   
     
     
         10 . The apparatus of  claim 8 , wherein the controller is further configured to:
 transmit or receive the additional data in accordance with a double data rate protocol.   
     
     
         11 . A method of data communication, comprising:
 configure a plurality of line interface circuits to provide a first group of wires in a plurality of wires for exchanging data when conducting a transaction over the plurality of wires, wherein the first group of wires includes at least three wires;   configure a frame duration for the transaction; and   configure a number of bits of the data to be transmitted in each frame of the transaction.   
     
     
         12 . The method of  claim 11 , wherein the frame duration is defined by a number of cycles of a clock signal used to control timing of data transmissions during the transaction. 
     
     
         13 . The method of  claim 11 , wherein the number of bits of the data is a multiple of a number of cycles of a clock signal used to control timing of the transaction. 
     
     
         14 . The method of  claim 11 , further comprising:
 using a symbol encoder to encode data in one or more sets of symbols transmitted over the first group of wires during the transaction, wherein each of the first group of wires carries one bit of a symbol in each symbol transmission interval provided in the transaction.   
     
     
         15 . The method of  claim 14 , wherein each set of symbols is transmitted in five symbol transmission intervals. 
     
     
         16 . The method of  claim 14 , further comprising:
 configuring the symbol encoder for a symbol encoding mode that uses the first group of wires to transmit each symbol.   
     
     
         17 . The method of  claim 16 , wherein the number of bits of the data to be transmitted in each frame of the transaction is determined by encoding efficiency of the symbol encoding mode. 
     
     
         18 . The method of  claim 11 , further comprising:
 configuring the plurality of line interface circuits to provide a second group of wires in the plurality of wires for transmitting or receiving additional data during the transaction.   
     
     
         19 . The method of  claim 18 , further comprising:
 transmitting or receiving the additional data in accordance with a single data rate protocol.   
     
     
         20 . The method of  claim 18 , further comprising:
 transmitting or receiving the additional data in accordance with a double data rate protocol.   
     
     
         21 . A non-transitory storage medium, comprising code for:
 configuring a plurality of line interface circuits to provide a first group of wires in a plurality of wires for exchanging data when conducting a transaction over the plurality of wires, wherein the first group of wires includes at least three wires;   configuring a frame duration for the transaction; and   configuring a number of bits of the data to be transmitted in each frame of the transaction.   
     
     
         22 . The non-transitory storage medium of  claim 21 , wherein the frame duration is defined by a number of cycles of a clock signal used to control timing of data transmissions during the transaction. 
     
     
         23 . The non-transitory storage medium of  claim 21 , wherein the number of bits of the data is a multiple of a number of cycles of a clock signal used to control timing of the transaction. 
     
     
         24 . The non-transitory storage medium of  claim 21 , further comprising code for:
 using a symbol encoder to encode data in one or more sets of symbols transmitted over the first group of wires during the transaction, wherein each of the first group of wires carries one bit of a symbol in each symbol transmission interval provided in the transaction.   
     
     
         25 . The non-transitory storage medium of  claim 24 , wherein each set of symbols is transmitted in five symbol transmission intervals. 
     
     
         26 . The non-transitory storage medium of  claim 21 , further comprising code for:
 configuring a symbol encoder for a symbol encoding mode that uses the first group of wires to transmit each symbol, wherein the number of bits of the data to be transmitted in each frame of the transaction is determined by encoding efficiency of the symbol encoding mode.   
     
     
         27 . The non-transitory storage medium of  claim 21 , further comprising code for:
 configuring the plurality of line interface circuits to provide a second group of wires in the plurality of wires for transmitting or receiving additional data during the transaction.   
     
     
         28 . An apparatus adapted for data communication, comprising:
 means for coupling the apparatus to a plurality of wires, the means for coupling configured to provide a first group of wires in the plurality of wires for exchanging data when the apparatus is conducting a transaction with another device; and   means for transmitting data during the transaction in frames, wherein the frames are configured with a frame duration and further configured with a number of bits of the data to be transmitted in each frame of the transaction.   
     
     
         29 . The apparatus of  claim 28 , wherein the frame duration is defined by a number of cycles of a clock signal used to control timing of data transmissions during the transaction, and wherein the number of bits of the data is a multiple of the number of cycles of the clock signal. 
     
     
         30 . The apparatus of  claim 28 , further comprising:
 means for encoding data in one or more sets of symbols transmitted over the first group of wires during the transaction, wherein each of the first group of wires carries one bit of a symbol in each symbol transmission interval provided in the transaction.

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