Systems and methods for fabricating superconducting integrated circuits

Abstract

Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

1 . A method for fabricating a superconducting integrated circuit, the method comprising:
 depositing a first wiring layer comprising a first material that is superconductive in a first range of temperatures, the first range of temperatures including a respective critical temperature;   patterning the first wiring layer to form a first set of one or more superconducting traces;   depositing a first dielectric layer;   polishing the first dielectric layer back to an upper surface of the first wiring layer;   depositing a passivation layer to overlie at least a portion of the first wiring layer, the passivation layer comprising a second material that is superconductive in a second range of temperatures, the second range of temperatures including a respective critical temperature;   patterning the passivation layer;   depositing a second dielectric layer to overlie at least a portion of the passivation metal layer;   patterning the second dielectric layer to expose at least a portion of the passivation layer;   depositing a second wiring to overlie at least a portion of the passivation layer, the second wiring layer comprising the second material that is superconductive in the second range of temperatures;   forming a first set of vias electrically coupling the second wiring layer to the passivation layer, the first set of vias comprising the second material that is superconductive in the second range of temperatures; and   patterning the second wiring layer to form a second set of one or more superconducting traces.   
     
     
         2 . The method of  claim 1  wherein depositing the first wiring layer comprising the first material that is superconductive in the first range of temperatures includes depositing the first wiring layer comprising the first material that is superconductive at a respective critical temperature that is different from a respective critical temperature of the second range of temperatures. 
     
     
         3 . The method of  claim 1  further comprising polishing the second dielectric layer back to an upper surface of the passivation metal layer and re-depositing the second dielectric layer, after depositing the second dielectric layer to overlie at least a portion of the passivation metal layer. 
     
     
         4 . The method of  claim 1  further comprising depositing a third dielectric layer to overlie at least a portion of the second wiring layer. 
     
     
         5 . The method of  claim 4  further comprising polishing the third dielectric layer back to the upper surface of the second wiring layer and re-depositing the third dielectric layer. 
     
     
         6 . The method of  claim 4  further comprising patterning the third dielectric layer to expose at least a portion of the second wiring layer. 
     
     
         7 . The method of  claim 6  further comprising depositing a third wiring layer to overlie the third dielectric layer, the third wiring layer comprising the second material that is superconductive in the second range of temperatures. 
     
     
         8 . The method of  claim 7  further comprising patterning the third wiring layer to form a third set of one or more superconducting traces. 
     
     
         9 . The method of  claim 8  further comprising forming a second set of vias electrically coupling the third wiring layer to the second wiring layer, the second set of vias comprising the second material that is superconductive in the second range of temperatures. 
     
     
         10 . The method of  claim 1  wherein depositing a first wiring layer includes depositing the first wiring layer to overlie an additional wiring layer, the additional wiring layer comprising the first material that is superconductive in the first range of temperatures. 
     
     
         11 . The method of  claim 1  wherein patterning the first wiring layer to form a first set of one or more superconducting traces includes patterning the first wiring layer to form at least one of: a magnetometer, a transformer, at least a portion of an on-chip shield. 
     
     
         12 . The method of  claim 1  wherein patterning the second wiring layer to form a second set of one or more superconducting traces includes patterning the second wiring layer to form at least one of: a qubit and a coupler. 
     
     
         13 . A superconducting integrated circuit comprising:
 a first wiring layer including a first set of one or more superconducting traces, the first wiring layer comprising a first material that is superconductive in a first range of temperatures;   a passivation layer overlying the first wiring layer, the passivation layer comprising a second material that is superconductive in a second range of temperatures;   a second wiring layer including a second set of one or more superconducting traces, the second wiring layer comprising the second material that is superconductive in the second range of temperatures;   a first set of vias electrically coupling the passivation layer to the second wiring layer, the first set of vias comprising the second material that is superconductive in the second range of temperatures;   a third wiring layer including a third set of one or more superconducting traces, the third wiring layer comprising the second material that is superconductive in the second range of temperatures; and   a second set of vias electrically coupling the second wiring layer to the third wiring layer, the second set of vias comprising the second material that is superconductive in the second range of temperatures.   
     
     
         14 . The superconducting integrated circuit of  claim 13  wherein the first range of temperatures and the second range of temperatures each include a respective critical temperature, and the critical temperature of the first range of temperatures is higher than the critical temperature of the second range of temperatures. 
     
     
         15 . The superconducting integrated circuit of  claim 14  wherein the first material is niobium, and the second material is aluminum. 
     
     
         16 . The superconducting integrated circuit of  claim 13  further comprising a substrate and a trilayer Josephson junction, the substrate carrying: the trilayer Josephson junction, the first wiring layer, the passivation layer, the second wiring layer, the first set of vias, the third wiring layer, and the second set of vias. 
     
     
         17 . The superconducting integrated circuit of  claim 16  further comprising a fourth wiring layer and a third set of vias each overlying the trilayer Josephson junction, the third set of vias electrically coupling the trilayer Josephson junction to the fourth wiring layer. 
     
     
         18 . The superconducting integrated circuit of  claim 17  further comprising a fifth wiring layer and a fourth set of vias each overlying the fourth wiring layer, the fourth set of vias electrically coupling the fourth wiring layer to the fifth wiring layer. 
     
     
         19 . The superconducting integrated circuit of  claim 13  further comprising a first dielectric layer interposed between the passivation layer and the second wiring layer, the first dielectric layer comprising silicon dioxide. 
     
     
         20 . The superconducting integrated circuit of  claim 19  further comprising a second dielectric layer interposed between the second wiring layer and the third wiring layer, the second dielectric layer comprising silicon dioxide. 
     
     
         21 . The superconducting integrated circuit of  claim 13  wherein the first wiring layer is thicker than the passivation layer. 
     
     
         22 . The superconducting integrated circuit of  claim 13  wherein the first set of one or more superconducting traces forms at least a portion of at least one of: an on-chip shield and a magnetometer. 
     
     
         23 . The superconducting integrated circuit of  claim 13  wherein the second set of one or more superconducting traces forms at least one of: a qubit, and a coupler. 
     
     
         24 . The superconducting integrated circuit of  claim 13  wherein the third set of one or more superconducting traces forms at least one of: a qubit and a coupler. 
     
     
         25 . A method for fabricating a superconducting integrated circuit, the method comprising:
 depositing a base electrode layer, the base electrode layer comprising a deposited top surface having a first roughness;   planarizing the base electrode layer, the base electrode layer subsequently comprising a planarized top surface having a second surface roughness, the second surface roughness being less than the first surface roughness;   depositing an insulating layer to overly at least a portion of the planarized top surface of the base electrode layer; and   depositing a counter electrode layer to overly at least a portion of the insulating layer.   
     
     
         26 . The method of  claim 25 , wherein planarizing the base electrode layer comprises a chemical-mechanical planarization process. 
     
     
         27 . The method of  claim 25 , wherein planarizing the base electrode layer comprises planarizing the base electrode layer such that the planarized top surface of the base electrode layer is atomically smooth. 
     
     
         28 . The method of  claim 25 , further comprising patterning the base electrode layer and depositing a first dielectric layer prior to planarizing the base electrode layer, and wherein planarizing the base electrode layer further comprises planarizing the dielectric layer. 
     
     
         29 . The method of  claim 25 , further comprising planarizing the counter electrode layer. 
     
     
         30 . The method of  claim 25 , wherein depositing a base electrode layer comprises depositing niobium, depositing a counter electrode layer comprises depositing niobium, and wherein depositing an insulating layer comprises depositing a layer of aluminum and oxidizing the layer of aluminum to form aluminum oxide.