Prebiasing circuitry for fast settlement of switching converter in a power loss protection system

Abstract

A power loss protection integrated circuit includes a VIN terminal, a VOUT terminal, an STR terminal, a switch circuit (eFuse), a control circuit, and a prebiasing circuit. In a normal mode, current flows from a power source, into VIN, through the eFuse, out of VOUT, and to the output node. A switching converter of which the control circuit is a part is disabled. If a switch over condition then occurs, the eFuse is turned off and the switching converter starts operating. The switching converter receives energy from STR and drives the output node. Switch over is facilitated by prebiasing. Prior to switch over, the prebiasing circuit prebiases a control loop node as a function of eFuse current flow prior to switch over. When the switching converter begins operating, the node is already prebiased for the proper amount of current to be supplied by the switching converter onto the output node.

What is claimed is: 
     
         1 . A power loss protection integrated circuit comprising:
 a voltage input (VIN) terminal;   a voltage output (VOUT) terminal;   a stored voltage (STR) terminal;   a current switch circuit operable in an on state and an off state, wherein:
 in the on state the current switch circuit provides a low resistance current path from the VIN terminal to the VOUT terminal; 
 in the off state the current switch circuit decouples the VIN terminal from the VOUT terminal; and 
 the current switch circuit outputs a sense current signal indicative of a magnitude of a current flow through the current switch circuit; 
   a switching converter control circuit operable in a buck on state, wherein in the buck on state the switching converter control circuit receives a voltage from the STR terminal and drives a regulated voltage onto the VOUT terminal; and   a prebiasing circuit that receives the sense current signal from the current switch circuit and is configured to drive a prebias signal to regulate a load current of the regulated voltage when the switching converter control circuit is in the buck on state.   
     
     
         2 . The power loss protection integrated circuit of  claim 1 , wherein the sense current signal is a current signal that has a magnitude proportional to a magnitude of the current flow through the current switch circuit. 
     
     
         3 . The power loss protection integrated circuit of  claim 1 , wherein the prebiasing circuit drives the prebias signal onto a control loop node of the switching converter control circuit which regulates the load current of the regulated voltage. 
     
     
         4 . The power loss protection integrated circuit of  claim 3 , wherein the prebias signal that the prebiasing circuit drives onto the control loop node has a magnitude that is a function of a magnitude of the current flow through the current switch circuit. 
     
     
         5 . The power loss protection integrated circuit of  claim 3 , wherein:
 the switching converter control circuit comprises an error amplifier; and   the control loop node is at an output of the error amplifier.   
     
     
         6 . The power loss protection integrated circuit of  claim 5 , wherein the error amplifier is coupled to drive the control loop node when the switching converter control circuit is in the buck on state. 
     
     
         7 . The power loss protection integrated circuit of  claim 6 , wherein the prebiasing circuit is disabled from driving the control loop node upon the switching converter control circuit entering the buck on state. 
     
     
         8 . The power loss protection integrated circuit of  claim 6 , wherein the prebias signal prebiases a voltage on the control loop node for when the switching converter control circuit enters the buck on state. 
     
     
         9 . The power loss protection integrated circuit of  claim 8 , wherein when the switching converter control circuit enters the buck on state the prebias signal is indicative of the magnitude of the current flow through the current switch circuit prior to the switching converter control circuit entering the buck on state. 
     
     
         10 . The power loss protection integrated circuit of  claim 1 , wherein the switching converter control circuit enters the buck on state when the current switch circuit enters the off state. 
     
     
         11 . The power loss protection integrated circuit of  claim 10 , wherein the prebiasing circuit drives the prebias signal onto a control loop node of the switching converter control circuit when the current switch circuit is in the on state. 
     
     
         12 . The power loss protection integrated circuit of  claim 11 , wherein the prebiasing circuit is disabled from driving any signal onto the control loop node if the switching converter control circuit is in the buck on state. 
     
     
         13 . The power loss protection integrated circuit of  claim 1 , wherein the prebias signal is a voltage signal. 
     
     
         14 . The power loss protection integrated circuit of  claim 1 , wherein the switching converter control circuit is further operable in a boost on state, wherein the switching converter control circuit outputs a current onto the STR terminal in the boost on state. 
     
     
         15 . The power loss protection integrated circuit of  claim 1 , wherein the STR terminal is coupled to a capacitor bank. 
     
     
         16 . The power loss protection integrated circuit of  claim 1 , wherein the STR terminal is adapted to couple to a capacitor external to the integrated circuit. 
     
     
         17 . The power loss protection integrated circuit of  claim 1 , wherein a switching converter comprises the switching converter control circuit as well as additional circuit components that are external to the integrated circuit. 
     
     
         18 . The power loss protection integrated circuit of  claim 1 , wherein the prebiasing circuit is configured to receive a digital logic enable signal, wherein the prebiasing circuit is enabled to drive the prebias signal if the digital logic enable signal has a first digital logic value. 
     
     
         19 . The power loss protection integrated circuit of  claim 18 , wherein the prebiasing circuit is disabled from driving the prebias signal if the digital logic enable signal has a second digital logic value. 
     
     
         20 . The integrated circuit of  claim 19 , further comprising a serial bus interface adapted to receive a switch over command from a serial bus and, in response, to cause the digital logic enable signal to transition from the first digital logic value to the second digital logic value.