Oxide formation in a plasma process

Abstract

A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasma oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.

What is claimed is: 
     
         1 . A non-planar memory device, comprising:
 a first channel disposed above a substrate, and a second channel disposed abutting the first channel, wherein the first and second channels are each made from a nanowire;   a tunneling layer formed to enclose each of the first and second channels individually;   a multi-layer charge storage layer disposed overlying each of the tunneling layers; and   a blocking structure disposed overlying each of the multi-layer charge storage layers, wherein the blocking structure is formed by plasma oxidation.