Avalanche photodiode image sensors

Abstract

An electronic device may include an array of pixels. Each pixel may include a first single photon avalanche photodiode circuit that generates a first output signal on a first conductive line, a second avalanche photodiode circuit that generates a second output signal on a second conductive line, and a logic NAND gate having a first input coupled to the first conductive line, a second input coupled to the second conductive line, and an output coupled to an output line. The logic NAND gate may generate a third output signal based on the first and second output signals that is independent of dark current generated by the avalanche photodiodes. The third output signal may be processed to generate range values that are further processed to generate three-dimensional images of a scene.

What is claimed is: 
     
         1 . An image sensor, comprising:
 a first photodiode coupled to an input of a first source follower, wherein the first source follower produces a first signal based on a first output from the first photodiode;   a second photodiode coupled to an input of a second source follower, wherein the second source follower produces a second signal based on a second output from the second photodiode;   a microlens, wherein the first photodiode is interposed between the second photodiode and the microlens; and   logic circuitry that receives the first signal and the second signal and that generates an output signal based on the first and second signals.   
     
     
         2 . The image sensor defined in  claim 1 , wherein the first and second photodiodes comprise avalanche photodiodes. 
     
     
         3 . The image sensor defined in  claim 1 , further comprising:
 a transistor coupled between the first and second photodiodes.   
     
     
         4 . The image sensor defined in  claim 3 , wherein the transistor has a first state in which the transistor is on and shorts the output of the first photodiode to the output of the second photodiode, and wherein the transistor has a second state in which the transistor is off and the output of the first photodiode is isolated from the output of the second photodiode. 
     
     
         5 . The image sensor defined in  claim 4 , wherein the image sensor has a first quantum efficiency when the transistor is in the first state and a second quantum efficiency when the transistor is in the second state, and wherein the first quantum efficiency is less than the second quantum efficiency. 
     
     
         6 . The image sensor defined in  claim 1 , further comprising:
 control circuitry that applies a reverse bias to the first and second photodiodes.   
     
     
         7 . The image sensor defined in  claim 1 , wherein the logic circuitry comprises a NAND gate, and the logic circuitry decreases effects of dark current in the first and second photodiodes. 
     
     
         8 . An electronic device, comprising:
 a first photodiode configured to generate a first output signal through a first node;   a second photodiode configured to generate a second output signal through a second node;   control circuitry that is configured to selectively couple and decouple the first and second nodes; and   a logic gate that is configured to generate a third output signal based on the first and second output signals.   
     
     
         9 . The electronic device defined in  claim 8 , further comprising:
 a source follower interposed between the first node and the logic gate, wherein the control circuitry adjusts a voltage applied to the source follower.   
     
     
         10 . The electronic device defined in  claim 8 , further comprising:
 a microlens, wherein the first and second photodiodes receive light through the microlens.   
     
     
         11 . The electronic device defined in  claim 8 , further comprising:
 a light source that emits a pulse of light, wherein the control circuitry generates range information based on a time delay between the emitted pulse of light and a pulse in the third output signal.   
     
     
         12 . The electronic device defined in  claim 11 , wherein the light source is configured to emit the pulse of light in a first direction and to emit an additional pulse of light in a second direction. 
     
     
         13 . The electronic device defined in  claim 1 , further comprising:
 a third photodiode configured to generate a fourth output signal;   a fourth photodiode configured to generate a fifth output signal, wherein the logic gate receives the fourth output signal and the fifth output signal and generates the third output signal based on the first, second, fourth, and fifth output signals, wherein the third output signal is independent of dark current generated by the first, second, third, and fourth photodiodes.   
     
     
         14 . The electronic device defined in  claim 13 , wherein the logic gate comprises majority vote logic circuitry. 
     
     
         15 . The electronic device defined in  claim 13 , wherein the logic gate comprises a logic NAND gate. 
     
     
         16 . The electronic device defined in  claim 13 , wherein the first, second, third, and fourth photodiodes are arranged in a pattern of two columns and two rows. 
     
     
         17 . The electronic device defined in  claim 13 , wherein the first, second, third, and fourth photodiodes are arranged in first, second, third, and fourth respective columns within a single row. 
     
     
         18 . An image sensor pixel array, comprising:
 a pixel that receives light;   a first photodiode in the pixel that generates a first output through a first source follower in response to the received light;   a second photodiode in the pixel that generates a second output through a second source follower in response to the received light; and   a logic gate that is configured to generate a third output signal based on the first and second output signals.   
     
     
         19 . The image sensor pixel array defined in  claim 18 , wherein the logic gates comprises a logic NAND gate that generates the third output signal by performing a logic NAND operation on the first and second output signals. 
     
     
         20 . The image sensor pixel array defined in  claim 18 , further comprising:
 control circuitry; and   a transistor coupled to the first and second photodiodes, wherein the control circuitry selectively couples and decouples the first and second photodiodes with the transistor.