Sampling circuit and sampling method

Abstract

Sampling circuits and methods for sampling are provided. In a first operating phase, sampling capacitors are coupled to inputs, and in a second operating phase, to a common-mode signal.

What is claimed is: 
     
         1 . A sampling circuit, comprising:
 a first input, which is configured to receive a first signal;   a second input, which is configured to receive a second signal;   a first sampling capacitor;   a second sampling capacitor;   a common-mode signal generating circuit, which is configured to generate a common-mode signal at a common mode signal node, wherein the common-mode signal corresponds to a common-mode component of the first signal and of the second signal; and   a switching circuit, which is configured to couple, in a first operating phase, a first terminal of the first sampling capacitor to the first input, and a first terminal of the second sampling capacitor to the second input, and in a second operating phase, to couple the first terminal of the first sampling capacitor and the first terminal of the second sampling capacitor to the common-mode signal node.   
     
     
         2 . The sampling circuit as claimed in  claim 1 , wherein the switching circuit is configured to decouple the first terminal of the first sampling capacitor from the first input, and to decouple the first terminal of the second sampling capacitor from the second input, in the second operating phase. 
     
     
         3 . The sampling circuit as claimed in  claim 1 , wherein the common-mode signal generating circuit is configured to sample the common-mode signal and to provide the sampled common-mode signal to the switching circuit. 
     
     
         4 . The sampling circuit as claimed in  claim 3 , wherein the common-mode signal generating circuit comprises a third sampling capacitor configured to sample the common-mode signal. 
     
     
         5 . The sampling circuit as claimed in  claim 1 , wherein the common-mode signal generating circuit comprises a divider circuit coupled between the first input and the second input. 
     
     
         6 . The sampling circuit as claimed in  claim 5 , wherein the common-mode signal generating circuit comprises a buffer circuit coupled to an output node of the divider circuit. 
     
     
         7 . The sampling circuit as claimed in  claim 5 , wherein the divider circuit comprises a resistive divider circuit. 
     
     
         8 . The sampling circuit as claimed in  claim 5 , wherein the divider circuit comprises a series circuit coupled between the first input and the second input, and the series circuit comprises a first resistor, a first diode-connected transistor, a second diode-connected transistor and a second resistor. 
     
     
         9 . The sampling circuit as claimed in  claim 8 , wherein the divider circuit comprises a third transistor and a fourth transistor, wherein a control terminal of the third transistor is connected to a control terminal of the first diode-connected transistor, and wherein a control terminal of the fourth transistor is connected to a control terminal of the second diode-connected transistor. 
     
     
         10 . The sampling circuit as claimed in  claim 5 , wherein the divider circuit comprises a capacitive divider circuit. 
     
     
         11 . The sampling circuit as claimed in  claim 10 , wherein the divider circuit comprises:
 a series circuit coupled between the first input and the second input, the series circuit comprising a first capacitor and a second capacitor; and   an initialization circuit configured to initialize the first capacitor and the second capacitor.   
     
     
         12 . The sampling circuit as claimed in  claim 1 , further comprising a processing circuit coupled to a second terminal of the first sampling capacitor and to a second terminal of the second sampling capacitor, wherein the processing circuit is configured to operate at a lower maximum voltage than the common-mode signal generating circuit and/or the switching circuit. 
     
     
         13 . The sampling circuit of  claim 12 , wherein the processing circuit comprises a differential amplifier. 
     
     
         14 . The sampling circuit as claimed in  claim 1 , wherein the common-mode signal generating circuit is configured to be disabled. 
     
     
         15 . A sampling method, comprising:
 in a first operating phase, coupling a first terminal of a first sampling capacitor to a first input signal node, and a first terminal of a second sampling capacitor to a second input signal node; and   in a second operating phase, coupling the first terminal of the first sampling capacitor and the first terminal of the second sampling capacitor to a common-mode signal node, wherein a common mode signal at the common-mode signal node provides a common-mode signal corresponding to a common-mode component of a first signal at the first input signal node and a second signal at the second input signal node.   
     
     
         16 . The sampling method as claimed in  claim 15 , further comprising sampling the common-mode signal to provide a sampled common-mode signal at the common-mode signal node, wherein in the second operating phase, the sampled common-mode signal is applied to the first terminal of the first sampling capacitor and to the first terminal of the second sampling capacitor. 
     
     
         17 . The sampling method as claimed in  claim 15 , further comprising generating the common-mode signal using a divider circuit having an input coupled to the first input signal node and to the second input signal node. 
     
     
         18 . The sampling method as claimed in  claim 15 , wherein a difference in a signal value of the first signal and a signal value of the second signal is less than one-tenth of the signal value of the first signal or the signal value of the second signal. 
     
     
         19 . A circuit, comprising:
 a voltage divider comprising a first resistor, a second resistor, a diode connected NMOS transistor and a diode connected PMOS transistor coupled in series between a first input node and a second input node;   a complementary source follower coupled between the voltage divider and a common-mode output node; and   a switching network coupled to the first input node, the second input node, the common-mode output node, a first sampling capacitor and a second sampling capacitor.   
     
     
         20 . The circuit of  claim 19 , wherein:
 the first resistor has a first terminal coupled to the first input node and a second terminal coupled to a gate and drain of the diode connected NMOS transistor;   a source of the diode connected NMOS transistor is coupled to a source of the diode connected PMOS transistor;   the second resistor has a first terminal coupled to the second input node and a second terminal coupled to a gate and drain of the diode connected PMOS transistor; and   the complementary source follower comprises:
 a first NMOS transistor having a gate coupled to the gate of the diode connected NMOS transistor and a source coupled to a common mode output node, and 
 a first PMOS transistor having a gate coupled to the gate of the first PMOS transistor and a source coupled to the common-mode output node. 
   
     
     
         21 . The circuit of  claim 20 , wherein the switching network comprises:
 a first switch coupled between the first input node and the first sampling capacitor;   a second switch coupled between the first sampling capacitor and the common-mode output node;   a third switch coupled between the common-mode output node and the second sampling capacitor; and   a fourth switch coupled between the second sampling capacitor and the second input node.   
     
     
         22 . The circuit of  claim 21 , wherein:
 the first switch comprises a PMOS transistor;   the second switch comprises an NMOS transistor;   the third switch comprises a PMOS transistor; and   the fourth switch comprises an NMOS transistor.