Extended message signaled interrupts (msi) message data

Abstract

Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

What is claimed is: 
     
         1 . A method of passing information in a Peripheral Component Interconnect (PCI) express (PCIe) system, comprising:
 receiving at a host a signal from a PCIe endpoint comprising:
 a header; and 
 a body comprising:
 extended message signaled interrupt (MSI) message data comprising a system level identifier for the PCIe endpoint set by the host and indicating interrupt authorization in at least one of a first sixteen bits; and 
 MSI message data in at least one of a second sixteen bits; 
 wherein the first sixteen bits are between the header and the second sixteen bits; 
 
   extracting, at a root complex of the host, the body from the signal to form an MSI vector with the extended MSI message data still in a body of the MSI vector; and   passing over an internal bus the MSI vector to an interrupt controller in the host with the extended MSI message data still in the body of the MSI vector.   
     
     
         2 . The method of  claim 1 , wherein receiving at the host the signal comprising the header comprises receiving at the host the signal comprising a requester identifier in the header. 
     
     
         3 . The method of  claim 1 , wherein receiving at the host the body comprising the extended MSI message data comprises receiving the body comprising interrupt priority information. 
     
     
         4 . The method of  claim 1 , further comprising extracting, at the interrupt controller, the system level identifier from the extended MSI message data prior to acting on the MSI message data. 
     
     
         5 . The method of  claim 1 , wherein receiving at the host the body comprising the extended MSI message data comprises receiving the body comprising additional message data. 
     
     
         6 . The method of  claim 1 , further comprising configuring the PCIe endpoint with the system level identifier prior to receiving at the host the signal. 
     
     
         7 . The method of  claim 1 , further comprising inquiring, from the host to the PCIe endpoint, whether the PCIe endpoint is capable of sending the extended MSI message data. 
     
     
         8 . The method of  claim 1 , further comprising configuring the interrupt controller in the host to use the extended MSI message data in the body of the MSI vector. 
     
     
         9 . The method of  claim 1 , wherein the internal bus comprises a system bus. 
     
     
         10 . A host in a Peripheral Component Interconnect (PCI) express (PCIe) system, comprising:
 an internal bus;   a PCIe bus interface configured to be coupled to a PCIe bus, wherein the PCIe bus interface is further configured to receive a signal from the PCIe bus comprising:
 a header; and 
 a body comprising:
 extended message signaled interrupt (MSI) message data in at least one of a first sixteen bits comprising a system level identifier for a PCIe endpoint set by the host; and 
 MSI message data in at least one of a second sixteen bits; 
 
   an interrupt controller coupled to the internal bus;   a memory management unit coupled to the internal bus; and   a root complex coupled to the PCIe bus interface and the memory management unit, wherein the root complex is configured to extract the body from the signal to form an MSI vector with the extended MSI message data still in a body of the MSI vector and pass the MSI vector to the interrupt controller with the extended MSI message data still in the body of the MSI vector through the memory management unit and the internal bus;   wherein the interrupt controller is configured to determine whether to act on the MSI message data based on the system level identifier.   
     
     
         11 . The host of  claim 10 , wherein the internal bus comprises a system bus. 
     
     
         12 . A Peripheral Component Interconnect (PCI) express (PCIe) system, comprising:
 a PCIe bus;   a PCIe slave comprising:
 a slave PCIe bus interface coupled to the PCIe bus; 
 a slave control system configured to:
 detect an interrupt need condition; 
 assemble a signal comprising:
 a header; and 
 a body comprising: 
  extended message signaled interrupt (MSI) message data in at least one of a first sixteen bits comprising a system level identifier for the PCIe slave set by a host and indicating interrupt authorization; and 
  MSI message data in at least one of a second sixteen bits; and 
 
 send the signal to the host over the PCIe bus; and 
 
   the host comprising:
 an internal bus; 
 a host PCIe bus interface coupled to the PCIe bus, wherein the host PCIe bus interface is further configured to receive the signal; 
 an interrupt controller coupled to the internal bus; and 
 a root complex coupled to the host PCIe bus interface, wherein the root complex is configured to extract the body from the signal to form an MSI vector with the extended MSI message data still in a body of the MSI vector and pass the MSI vector to the interrupt controller with the extended MSI message data still in the body of the MSI vector through the internal bus. 
   
     
     
         13 . The PCIe system of  claim 12 , wherein the internal bus comprises a system bus. 
     
     
         14 . A method of identifying a signal source in a Peripheral Component Interconnect (PCI) express (PCIe) system, comprising:
 receiving at a host a signal from a Peripheral Component Interconnect (PCI) express (PCIe) endpoint comprising:
 a header having a requester identifier; and 
 a body comprising:
 a source identifier for the PCIe endpoint set by the host in at least one of a first sixteen bits; and 
 message signaled interrupt (MSI) message data in at least one of a second sixteen bits; 
 
   at a root complex of the host, removing the requester identifier;   extracting the body to form an MSI vector with the source identifier still in a body of the MSI vector; and   passing over an internal bus the MSI vector to an interrupt controller in the host with the source identifier still in the body of the MSI vector.   
     
     
         15 . The method of  claim 14 , further comprising using the source identifier at the interrupt controller to verify the PCIe endpoint as authorized to request an interrupt. 
     
     
         16 . The method of  claim 14 , further comprising initiating a capability query at the host to the PCIe endpoint. 
     
     
         17 . The method of  claim 16 , further comprising receiving a response to the capability query from the PCIe endpoint indicating the PCIe endpoint is capable of using the source identifier in the body of the signal. 
     
     
         18 . The method of  claim 17 , further comprising instructing the PCIe endpoint to enable use of the source identifier in the body of the signal. 
     
     
         19 . The method of  claim 14 , further comprising configuring the interrupt controller to read the source identifier in the body of the MSI vector. 
     
     
         20 . A method of identifying a signal source, comprising:
 receiving at a host a signal from a Peripheral Component Interconnect (PCI) express (PCIe) endpoint comprising:
 a header having a requester identifier; and 
 a body comprising:
 a system level identifier for the PCIe endpoint set by the host in at least one of a first sixteen bits; and 
 message signaled interrupt (MSI) message data in at least one of a second sixteen bits; 
 
   at a root complex of the host, removing the requester identifier;   extracting the body to form an MSI vector with the system level identifier still in a body of the MSI vector; and   passing over an internal bus the MSI vector to an interrupt controller in the host with the system level identifier still in the body of the MSI vector.   
     
     
         21 . The method of  claim 20 , wherein the internal bus comprises a system bus. 
     
     
         22 . A method of passing information in a Peripheral Component Interconnect (PCI) express (PCIe) system, comprising:
 receiving at a host, from a PCIe endpoint, a signal comprising:
 a header; and 
 a body, wherein the body comprises:
 a first sixteen reserved bits having extended message signaled interrupt (MSI) message data in at least one of the first sixteen reserved bits and comprising a system level identifier for the PCIe endpoint set by the host; and 
 a second sixteen bits having MSI message data in at least one of the second sixteen bits; 
 
   extracting, at a root complex of the host, the body from the signal to form an MSI vector with the extended MSI message data still in a body of the MSI vector;   passing over an internal bus the MSI vector to an interrupt controller in the host with the extended MSI message data still in the body of the MSI vector; and   determining, at the interrupt controller, whether to act on the MSI message data based on the system level identifier.