Low power memory device with column and row line switches for specific memory cells

Abstract

The present invention provides a memory device. The memory device comprises a plurality of word lines; and at least one memory unit comprising a plurality of memory cell groups; at least one bit line; a plurality of local bit lines; a column word line elongated along the second direction; and a plurality of column switches, each of the column switches configured to control conduction between the at least one bit line and one of the local bit lines; wherein a plurality of the memory units are arranged along the first direction, a number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively.

What is claimed is: 
     
         1 . A memory device, comprising:
 a plurality of word lines elongated along a first direction; and   at least one memory unit comprising:
 a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; 
 at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; 
 a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; 
 a column word line elongated along the second direction; 
 a plurality of row word lines elongated along the first direction; 
 a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the column word line, a first terminal, and a second terminal, each of the column switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; and 
 a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a row word line, a first terminal, and a second terminal, each of the row switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; 
 wherein one of the column switches and one of the row switches are electrically coupled in series between the at least one bit line and one of the local bit line. 
   
     
     
         2 . The memory device of  claim 1 , wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line. 
     
     
         3 . The memory device of  claim 1 , wherein the plurality of column switches and the plurality of row switches are transistors. 
     
     
         4 . The memory device of  claim 1 , wherein the memory device comprises a plurality of the memory units arranged along the first direction, a predetermined number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively. 
     
     
         5 . The memory device of  claim 1 , wherein in the at least one memory unit, the plurality of memory cell groups arranged along the second direction are electrically isolated from each other by the plurality of row switches. 
     
     
         6 . The memory device of  claim 1 , wherein the memory device comprises a plurality memory blocks arranged along the first direction, each memory block comprises a plurality of memory units arranged along the first direction, the plurality memory blocks receive a plurality of column word line signals, respectively, and column switches within a first memory block are controlled by a first column word line signal among the plurality of column word line signals. 
     
     
         7 . The memory device of  claim 6 , wherein a plurality of second memory units within a second memory block and a plurality of third memory units within a third memory block are disposed in an interleaved manner. 
     
     
         8 . A memory device, comprising:
 a plurality of word lines elongated along a first direction; and   at least one memory unit comprising:
 a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; 
 at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; 
 a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; 
 a column word line elongated along the second direction; and 
 a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the column word line, a first terminal coupled to one of the local bit lines, and a second terminal coupled to the at least one bit line, each of the column switches configured to control conduction between the at least one bit line and one of the local bit lines; 
   wherein a plurality of the memory units are arranged along the first direction, a number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively.   
     
     
         9 . The memory device of  claim 8 , wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line. 
     
     
         10 . The memory device of  claim 8 , wherein the plurality of column switches and the plurality of row switches are transistors. 
     
     
         11 . The memory device of  claim 8 , wherein the at least one memory unit further comprises:
 a plurality of row word lines elongated along the first direction; and   a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a corresponding row word line;   wherein each of the row switches and a corresponding column switch are coupled between one of the memory cell groups and the at least one bit line in series;   wherein in the at least one memory unit, the plurality of memory cell groups arranged along the second direction are electrically isolated from each other by the plurality of row switches.   
     
     
         12 . The memory device of  claim 8 , wherein the memory device comprises a plurality memory blocks arranged along the first direction, each memory block comprises a plurality of memory units arranged along the first direction, the plurality memory blocks receive a plurality of column word line signals, respectively, and column switches within a first memory block are controlled by a first column word line signal among the plurality of column word line signals. 
     
     
         13 . The memory device of  claim 8 , wherein a plurality of second memory units within a second memory block and a plurality of third memory units within a third memory block are disposed in an interleaved manner. 
     
     
         14 . A memory device, comprising:
 a plurality of word lines elongated along a first direction; and   at least one memory unit comprising:
 a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; 
 at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; 
 a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; 
 a column word line elongated along the second direction; and 
 a plurality of row word lines elongated along the first direction; 
   wherein the selected memory cell is selected by a corresponding word line, the column word line and a corresponding row word line.   
     
     
         15 . The memory device of  claim 14 , wherein the memory device comprises a plurality memory blocks arranged along the first direction, each memory block comprises a plurality of memory units arranged along the first direction, the plurality memory blocks receive a plurality of column word line signals, respectively, and column switches within a first memory block are controlled by a first column word line signal among the plurality of column word line signals. 
     
     
         16 . The memory device of  claim 14 , wherein a plurality of second memory units within a second memory block and a plurality of third memory units within a third memory block are disposed in an interleaved manner.