Low power adc sampling in a digital power controller

Abstract

According to certain aspects, the present embodiments provide a solution for sampling and converting an analog signal at high frequencies but with low power consumption. In some embodiments, a low power, low resolution, AC coupled ADC is used to track the high frequency component of the analog input signal, in parallel with a high resolution ADC to sense the DC signal at a significantly lower sample rate. According to some aspects, the AC coupled ADC requires no reference or a low resolution reference. In these and other embodiments, a plurality of low resolution, low power ADCs having a high sampling rate may be time multiplexed together with a precision ADC at a low sampling rate.

What is claimed is: 
     
         1 . An apparatus for sampling signals in a power controller, comprising:
 a first analog-to-digital converter (ADC) configured to sample an input signal at a first sample rate, the input signal being associated with a sense signal in the power controller;   a second ADC configured to sample the input signal at a second higher sample rate; and   a summer that combines the outputs of the first ADC and the second ADC to produce a measured value of the sense signal at the second sample rate.   
     
     
         2 . The apparatus of  claim 1 , wherein the second ADC is AC coupled to the input signal. 
     
     
         3 . The apparatus of  claim 1 , wherein the second ADC comprises one or more capacitors that are reset with the output of the first ADC at the first sample rate to as to zero the second ADC. 
     
     
         4 . The apparatus of  claim 1 , wherein the second ADC has a precision that is lower than the first ADC. 
     
     
         5 . The apparatus of  claim 1 , wherein the second ADC uses a power supply voltage as a reference. 
     
     
         6 . The apparatus of  claim 1 , wherein the sense signal comprises an inductor current sense signal. 
     
     
         7 . The apparatus of  claim 1 , wherein the sense signal comprises an output voltage sense signal. 
     
     
         8 . An apparatus for sampling signals in a power controller, comprising:
 a first analog-to-digital converter (ADC) configured to sample a plurality of input signals, each at a first sample rate;   a plurality of second ADCs, each second ADC being configured to sample a respective one of the input signals at a second higher sample rate; and   a plurality of summers that combine the outputs of the first ADC and respective ones of the second ADCs to produce measured values of the plurality of input signals at the second sample rate.   
     
     
         9 . The apparatus of  claim 8 , wherein each of the second ADCs is AC coupled to the input signal. 
     
     
         10 . The apparatus of  claim 8 , wherein each of the second ADCs comprises one or more capacitors that are reset with the output of the first ADC at the first sample rate to as to zero the second ADC. 
     
     
         11 . The apparatus of  claim 8 , wherein each of the second ADCs has a precision that is lower than the first ADC. 
     
     
         12 . The apparatus of  claim 8 , wherein each of the second ADCs uses a power supply voltage as a reference. 
     
     
         13 . The apparatus of  claim 8 , wherein the first ADC is a telemetry ADC for the power controller. 
     
     
         14 . A method for sampling signals in a power controller, comprising:
 sampling an input signal with a first analog-to-digital converter (ADC) at a first sample rate, the input signal being associated with a sense signal in the power controller;   sampling the input signal with a second ADC at a second higher sample rate;   zeroing the second ADC with an output of the first ADC at the first sample rate; and   combining the outputs of the first ADC and the second ADC to produce a measured value of the sense signal at the second sample rate.   
     
     
         15 . The method of  claim 14 , wherein the second ADC is AC coupled to the input signal. 
     
     
         16 . The method of  claim 14 , wherein the second ADC comprises one or more capacitors that are reset with the output of the first ADC at the first sample rate to as to zero the second ADC. 
     
     
         17 . The method of  claim 14 , wherein the second ADC has a precision that is lower than the first ADC. 
     
     
         18 . The method of  claim 14 , wherein the second ADC uses a power supply voltage as a reference. 
     
     
         19 . The method of  claim 14 , wherein the sense signal comprises an inductor current sense signal. 
     
     
         20 . The method of  claim 14 , wherein the sense signal comprises an output voltage sense signal.