Data-plane stateful processing units in packet processing pipelines

Abstract

A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

What is claimed is: 
     
         1 . Circuitry for use in a network switch, the network switch being for use, when the network switch is in operation, in generating, based at least in part upon at least one received packet, at least one outgoing packet, the circuitry comprising:
 at least one hardware processor-based packet-processing pipeline comprising a plurality of pipeline stages that are programmable, at least in part, the at least one hardware processor-based packet-processing pipeline being for use in (1) modifying, at least in part, the at least one received packet to generate the at least one outgoing packet, and (2) forwarding the at least one outgoing packet from the network switch, the plurality of pipeline stages comprising:
 at least one parser stage to parse and identify, at least in part, header field information of the at least one received packet; 
 match-action stages to match and modify, at least in part, the header field information based, at least in part, upon match-action table information, to generate modified header field information; and 
 at least one other stage to generate, at least in part, the at least one outgoing packet based, at least in part upon the modified header field information; 
   wherein:
 when the circuitry is in operation, the circuitry is to receive at least one set of instructions for use in programming, at least in part, the plurality of pipeline stages to perform packet processing algorithms to generate the at least one outgoing packet; 
 the at least one set of instructions is to be generated based, at least in part, upon compilation of text-based source code that specifies, at least in part, the packet processing algorithms; and 
 when the circuitry is in the operation, the circuitry is to collect packet-related information for use in network management-related operations. 
   
     
     
         2 . The circuitry of  claim 1 , wherein:
 the text-based source code is based, at least in part, upon:
 a subset of C programming language; 
 P4 programming language; or 
 Python programming language. 
   
     
     
         3 . The circuitry of  claim 2 , wherein:
 the subset of C programming language comprises struct fields.   
     
     
         4 . The circuitry of  claim 3 , wherein:
 an application specific integrated circuit comprises the at least one hardware processor-based packet-processing pipeline.   
     
     
         5 . The circuitry of  claim 4 , wherein:
 the subset of C programming language also comprises an if-then statement.   
     
     
         6 . The circuitry of  claim 5 , wherein:
 the header field information of the at least one received packet comprises packet flow five-tuple-related information.   
     
     
         7 . The circuitry of  claim 6 , wherein:
 the at least one set of instructions is usable with a configuration synthesis tool for use in synthesizing configuration of at least a portion of the at least one hardware processor-based packet-processing pipeline.   
     
     
         8 . The circuitry of  claim 7 , wherein:
 the compilation is to be generated, at least in part, by a compiler; and   in event that the compiler is unable to generate the at least one set of instructions for the at least one hardware processor-based packet-processing pipeline, the compiler is to indicate compiler error.   
     
     
         9 . The circuitry of  claim 7 , wherein:
 the configuration synthesis tool is to perform synthesis and executability operations related to different pipeline processor designs.   
     
     
         10 . The circuitry of  claim 7 , wherein:
 the configuration synthesis tool is to perform operations related to generating the at least one set of instructions based, at least in part, upon a user-specified template or partial program; and   the operations relate, at least in part, to supplementing the user-specified template or partial program.   
     
     
         11 . The circuitry of  claim 6 , wherein:
 the packet-related information relates, at least in part, to packet and ports; and   the network management-related operations relate, at least in part, to managing the network switch and a network.   
     
     
         12 . The circuitry of  claim 6 , further comprising:
 the network switch.   
     
     
         13 . At least one non-transient machine readable storage medium storing program instructions for being executed by circuitry for use in a network switch, the network switch being for use, when the network switch is in operation, in generating, based at least in part upon at least one received packet, at least one outgoing packet, the circuitry comprising at least one hardware processor-based packet-processing pipeline that comprises a plurality of pipeline stages that are programmable, at least in part, the at least one hardware processor-based packet-processing pipeline being for use in (1) modifying, at least in part, the at least one received packet to generate the at least one outgoing packet and (2) forwarding the at least one outgoing packet from the network switch, the program instructions, when executed, resulting in performance of operations comprising:
 parsing and identifying, at least in part, header field information of the at least one received packet by at least one parser stage of the plurality of pipeline stages;   matching and modifying, at least in part, the header field information by match-action stages of the plurality of pipeline stages, the matching and the modifying being (1) based, at least in part, upon match-action table information and (2) to generate modified header field information; and   generating, at least in part, the at least one outgoing packet by at least one other stage of the plurality of pipeline stages, the generating of the at least one outgoing packet being based, at least in part, upon the modified header information;   wherein:
 when the circuitry is in operation, the circuitry is to receive at least one set of instructions for use in programming, at least in part, the plurality of pipeline stages to perform packet processing algorithms to generate the at least one outgoing packet; 
 the at least one set of instructions is to be generated based, at least in part, upon compilation of text-based source code that specifies, at least in part, the packet processing algorithms; and 
 when the circuitry is in the operation, the circuitry is to collect packet-related information for use in network management operations. 
   
     
     
         14 . The at least one non-transient machine readable storage medium of  claim 13 , wherein:
 the text-based source code is based, at least in part, upon:
 a subset of C programming language; 
 P4 programming language; or 
 Python programming language. 
   
     
     
         15 . The at least one non-transient machine readable storage medium of  claim 14 , wherein:
 the subset of C programming language comprises struct fields.   
     
     
         16 . The at least one non-transient machine readable storage medium of  claim 15 , wherein:
 an application specific integrated circuit comprises the at least one hardware processor-based packet-processing pipeline.   
     
     
         17 . The at least one non-transient machine readable storage medium of  claim 16 , wherein:
 the subset of C programming language also comprises an if-then statement.   
     
     
         18 . The at least one non-transient machine readable storage medium of  claim 17 , wherein:
 the header field information of the at least one received packet comprises packet flow five-tuple-related information.   
     
     
         19 . The at least one non-transient machine readable storage medium of  claim 18 , wherein:
 the at least one set of instructions is usable with a configuration synthesis tool for use in synthesizing configuration of at least a portion of the at least one hardware processor-based packet-processing pipeline.   
     
     
         20 . The at least one non-transient machine readable storage medium of  claim 19 , wherein:
 the compilation is to be generated, at least in part, by a compiler; and   in event that the compiler is unable to generate the at least one set of instructions for the at least one hardware processor-based packet-processing pipeline, the compiler is to indicate compiler error.   
     
     
         21 . The at least one non-transient machine readable storage medium of  claim 19 , wherein:
 the configuration synthesis tool is to perform synthesis and executability operations related to different pipeline processor designs.   
     
     
         22 . The at least one non-transient machine readable storage medium of  claim 19 , wherein:
 the configuration synthesis tool is to perform other operations related to generating the at least one set of instructions based, at least in part, upon a user-specified template or partial program; and   the other operations relate, at least in part, to supplementing the user-specified template or partial program.   
     
     
         23 . The at least one non-transient machine readable storage medium of  claim 18 , wherein:
 the packet-related information relates, at least in part, to packet and ports; and   the network management-related operations relate, at least in part, to managing the network switch and a network.   
     
     
         24 . A method implemented, at least in part, by circuitry for use in a network switch, the network switch being for use, when the network switch is in operation, in generating, based at least in part upon at least one received packet, at least one outgoing packet, the circuitry comprising at least one hardware processor-based packet-processing pipeline that comprises a plurality of pipeline stages that are programmable, at least in part, the at least one hardware processor-based packet-processing pipeline being for use in (1) modifying, at least in part, the at least one received packet to generate the at least one outgoing packet and (2) forwarding the at least one outgoing packet from the network switch, the method comprising:
 parsing and identifying, at least in part, header field information of the at least one received packet by at least one parser stage of the plurality of pipeline stages;   matching and modifying, at least in part, the header field information by match-action stages of the plurality of pipeline stages, the matching and the modifying being (1) based, at least in part, upon match-action table information and (2) to generate modified header field information; and   generating, at least in part, the at least one outgoing packet by at least one other stage of the plurality of pipeline stages, the generating of the at least one outgoing packet being based, at least in part, upon the modified header information;   wherein:
 when the circuitry is in operation, the circuitry is to receive at least one set of instructions for use in programming, at least in part, the plurality of pipeline stages to perform packet processing algorithms to generate the at least one outgoing packet; 
 the at least one set of instructions is to be generated based, at least in part, upon compilation of text-based source code that specifies, at least in part, the packet processing algorithms; and 
 when the circuitry is in the operation, the circuitry is to collect packet-related information for use in network management operations. 
   
     
     
         25 . The method of  claim 24 , wherein:
 the text-based source code is based, at least in part, upon:
 a subset of C programming language; 
 P4 programming language; or 
 Python programming language. 
   
     
     
         26 . The method of  claim 25 , wherein:
 the subset of C programming language comprises struct fields.   
     
     
         27 . The method of  claim 26 , wherein:
 an application specific integrated circuit comprises the at least one hardware processor-based packet-processing pipeline.   
     
     
         28 . The method of  claim 27 , wherein:
 the subset of C programming language also comprises an if-then statement.   
     
     
         29 . The method of  claim 28 , wherein:
 the header field information of the at least one received packet comprises packet flow five-tuple-related information.   
     
     
         30 . The method of  claim 29 , wherein:
 the at least one set of instructions is usable with a configuration synthesis tool for use in synthesizing configuration of at least a portion of the at least one hardware processor-based packet-processing pipeline.   
     
     
         31 . The method of  claim 30 , wherein:
 the compilation is to be generated, at least in part, by a compiler; and   in event that the compiler is unable to generate the at least one set of instructions for the at least one hardware processor-based packet-processing pipeline, the compiler is to indicate compiler error.   
     
     
         32 . The method of  claim 30 , wherein:
 the configuration synthesis tool is to perform synthesis and executability operations related to different pipeline processor designs.   
     
     
         33 . The method of  claim 30 , wherein:
 the configuration synthesis tool is to perform other operations related to generating the at least one set of instructions based, at least in part, upon a user-specified template or partial program; and   the other operations relate, at least in part, to supplementing the user-specified template or partial program.   
     
     
         34 . The method of  claim 29 , wherein:
 the packet-related information relates, at least in part, to packet and ports; and   the network management-related operations relate, at least in part, to managing the network switch and a network.   
     
     
         35 . At least one non-transient machine readable storage medium storing program instructions for being executed by at least one processor, the program instructions when executed by the at least one processor resulting in the at least one processor being configured to perform operations comprising:
 generating, at least in part, at least one set of instructions for use in programming, at least in part, a plurality of pipeline stages, the generating being based, at least in part, upon compilation of text-based source code that specifies, at least in part, packet processing algorithms to be performed by the plurality of pipeline stages, the plurality of pipeline stages being comprised in at least one hardware processor-based packet-processing pipeline comprised in circuitry that is for use in a network switch, the network switch being for use, when the network switch is in operation, in generating, based at least in part upon at least one received packet, at least one outgoing packet, the at least one outgoing packet to be generated based, at least in part, of the packet processing algorithms;   wherein:
 the at least one hardware processor-based packet-processing pipeline is for use in (1) modifying, at least in part, the at least one received packet to generate the at least one outgoing packet and (2) forwarding the at least one outgoing packet from the network switch; 
 the plurality of pipeline stages comprises:
 at least one parser stage to parse and identify, at least in part, header field information of the at least one received packet; 
 match-action stages to match and modify, at least in part, the header field information based, at least in part, upon match-action table information, to generate modified header field information; and 
 at least one other stage to generate, at least in part, the at least one outgoing packet based, at least in part upon the modified header field information; and 
 
 when the circuitry is in the operation, the circuitry is to collect packet-related information for use in network management-related operations. 
   
     
     
         36 . The at least one non-transient machine readable storage medium of  claim 35 , wherein:
 the text-based source code is based, at least in part, upon:
 a subset of C programming language; 
 P4 programming language; or 
 Python programming language. 
   
     
     
         37 . The at least one non-transient machine readable storage medium of  claim 36 , wherein:
 the subset of C programming language comprises struct fields.   
     
     
         38 . The at least one non-transient machine readable storage medium of  claim 37 , wherein:
 an application specific integrated circuit comprises the at least one hardware processor-based packet-processing pipeline.   
     
     
         39 . The at least one non-transient machine readable storage medium of  claim 38 , wherein:
 the subset of C programming language also comprises an if-then statement.   
     
     
         40 . The at least one non-transient machine readable storage medium of  claim 39 , wherein:
 the header field information of the at least one received packet comprises packet flow five-tuple-related information.   
     
     
         41 . The at least one non-transient machine readable storage medium of  claim 40 , wherein:
 the at least one set of instructions is usable with a configuration synthesis tool for use in synthesizing configuration of at least a portion of the at least one hardware processor-based packet-processing pipeline.   
     
     
         42 . The at least one non-transient machine readable storage medium of  claim 41 , wherein:
 the compilation is to be generated, at least in part, by a compiler; and   in event that the compiler is unable to generate the at least one set of instructions for the at least one hardware processor-based packet-processing pipeline, the compiler is to indicate compiler error.   
     
     
         43 . The at least one non-transient machine readable storage medium of  claim 41 , wherein:
 the configuration synthesis tool is to perform synthesis and executability operations related to different pipeline processor designs.   
     
     
         44 . The at least one non-transient machine readable storage medium of  claim 41 , wherein:
 the configuration synthesis tool is to perform other operations related to generating the at least one set of instructions based, at least in part, upon a user-specified template or partial program; and   the other operations relate, at least in part, to supplementing the user-specified template or partial program.   
     
     
         45 . The at least one non-transient machine readable storage medium of  claim 40 , wherein:
 the packet-related information relates, at least in part, to packet and ports; and   the network management-related operations relate, at least in part, to managing the network switch and a network.