Area and power efficient circuits for high-density standard cell libraries

Abstract

Example embodiments provide a four input multiplexer integrated circuit (MXT4) associated with an integrated circuit (IC) and a method for reducing area and power of an integrated circuit (IC) using a MXT4, the MXT4 including a complementary signal generator circuit configured to receive first and second selection signals and to generate first and second complementary selection signals based on respective ones of the first and the second selection signals; and a p-type metal oxide semiconductor (PMOS) and an n-type metal oxide semiconductor (NMOS) stack switch circuit configured to transmit at least one input signal to an output based on the first and the second selection signals and the first and the second complementary selection signals.

What is claimed is: 
     
         1 . A four input multiplexer integrated circuit (MXT4) associated with an integrated circuit (IC), the MXT4 comprising:
 a complementary signal generator circuit configured to receive first and second selection signals and to generate first and second complementary selection signals based on respective ones of the first and the second selection signals; and   a p-type metal oxide semiconductor (PMOS) and an n-type metal oxide semiconductor (NMOS) stack switch circuit configured to transmit at least one input signal to an output based on the first and the second selection signals and the first and the second complementary selection signals.   
     
     
         2 . The MXT4 of  claim 1 , wherein the complementary signal generator circuit includes one or more inverters. 
     
     
         3 . The MTX4 of  claim 2 , wherein the one or more inverters of the complementary signal generator circuit include two inverters configured to receive the respective ones of the first and the second selection signals without the first and the second input signals being passed through buffers, and to generate the first and the second complementary selection signals. 
     
     
         4 . The MTX4 of  claim 1 , wherein the PMOS and NMOS stack switch circuit is configured to receive first to fourth input signals, and to transmit one of the first to the fourth input signals to the output based on the first and the second selection signals and the first and the second complementary selection signals. 
     
     
         5 . The MTX4 of  claim 4 , wherein the PMOS and NMOS stack switch circuit is configured to transmit one of the first to the fourth input signals to the output without the first to the fourth input signal being passed through a transmission gate. 
     
     
         6 . The MTX4 of  claim 4 , wherein the PMOS and NMOS stack switch circuit comprises:
 first to fourth PMOS transistors connected to a source, the first to fourth PMOS transistors configured to receive the first to the fourth input signals, respectively; and   first to fourth NMOS transistors connected to a ground, the first to fourth NMOS transistors configured to receive the first to the fourth input signals, respectively, wherein
 the first to the fourth input signals are only provided to a circuit including the first to the fourth PMOS transistors and the first to the fourth NMOS transistors. 
   
     
     
         7 . The MTX of  claim 6 , wherein the PMOS and NMOS stack switch circuit further comprises:
 fifth and sixth PMOS transistors connected to the first and the third PMOS transistors in series, respectively, the fifth and sixth PMOS transistors configured to receive the first selection signal;   seventh and eighth PMOS transistors connected to the second and the fourth PMOS transistors in series, respectively, the seventh and eighth PMOS transistors configured to receive the first complementary selection signal;   fifth and sixth NMOS transistors connected to the first and the third NMOS transistors in series, respectively, the fifth and sixth NMOS transistors configured to receive the first complementary selection signal; and   seventh and eighth NMOS transistors connected to the second and the fourth NMOS transistors in series, respectively, the seventh and eighth NMOS transistors configured to receive the first selection signal, wherein
 the first selection signal and the first complementary selection signal are only provided to a circuit including the fifth to the eighth PMOS transistors and the fifth to the eighth NMOS transistors. 
   
     
     
         8 . The MTX of  claim 7 , wherein the PMOS and NMOS stack switch circuit further comprises:
 a ninth PMOS transistor connected to the fifth and the seventh PMOS transistors at a first node, the ninth PMOS transistor configured to receive the second selection signal;   a tenth PMOS transistor connected to the sixth and the eighth PMOS transistors at a second node, the tenth PMOS transistor configured to receive the second complementary selection signal;   a ninth NMOS transistor connected to the fifth and the seventh NMOS transistors at a third node, the ninth NMOS transistor configured to receive the second complementary selection signal; and   a tenth NMOS transistor connected to the sixth and the eighth NMOS transistors at a fourth node, the tenth NMOS transistor configured to receive the second selection signal, wherein
 the second selection signal and the second complementary selection signal are only provided to a circuit including the ninth and the tenth PMOS transistors and the ninth and the tenth NMOS transistors. 
   
     
     
         9 . The MTX of  claim 8 , wherein the ninth and the tenth PMOS transistors and the ninth and the tenth NMOS transistors are connected to a fifth node, and the PMOS and NMOS stack switch circuit further comprises:
 an inverter having an input connected to the fifth node, the inverter configured to generate an output signal at the output.   
     
     
         10 . A method for reducing area and power of an integrated circuit (IC) using a four input multiplexer Integrated circuit (MXT4), the method comprising:
 generating, by a complementary signal generator circuit, first and second complementary selection signals based on respective ones of first and second selection signals; and   transmitting, by a PMOS and a NMOS stack switch circuit, at least one input signal to an output based on the first and the second selection signals and the first and the second complementary selection signals.   
     
     
         11 . The method of  claim 10 , wherein the generating the first and the second complementary selection signals comprises:
 generating the first and the second complementary selection signals based on the respective ones of first and second selection signals without the first and the second selection signals passing through buffers.   
     
     
         12 . The method of  claim 10 , wherein the transmitting the at least one input signal to the output comprises:
 receiving first to fourth input signals, the first and the second selection signals, and the first and the second complementary signals; and   transmitting one of the first to the fourth input signals to the output based on the first and the second selection signals, and the first and the second complementary signals.   
     
     
         13 . The method of  claim 12 , wherein the transmitting one of the first to the fourth input signals to the output comprises:
 transmitting one of the first to the fourth input signals to the output based on the first and the second selection signals, and the first and the second complementary signals without the first to the fourth input signal being passed through a transmission gate.   
     
     
         14 . The method of  claim 12 , wherein the receiving the first to the fourth input signals, the first and the second selection signals, and the first and the second complementary signals comprises:
 providing the first to the fourth input signals to first to fourth PMOS transistors, respectively; and   providing the first to the fourth input signals to first to fourth NMOS transistors, respectively, wherein
 the first to the fourth input signals are only provided to a circuit including the first to the fourth PMOS transistors and the first to the fourth NMOS transistors. 
   
     
     
         15 . The method of  claim 14 , wherein the receiving the first to the fourth input signals, the first and the second selection signals, and the first and the second complementary signals comprises:
 providing the first selection signal to fifth and sixth PMOS transistors connected to the first and the third PMOS transistors, respectively;   providing the first complementary selection signal to seventh and eighth PMOS transistors connected to the second and the fourth PMOS transistors, respectively;   providing the first complementary selection signal to fifth and sixth NMOS transistors connected to the first and the third NMOS transistors, respectively; and   providing the first selection signal to seventh and eighth NMOS transistors connected to the second and the fourth NMOS transistors, respectively, wherein
 the first selection signal and the first complementary selection signal are only provided to a circuit including the fifth to the eighth PMOS transistors and the fifth to the eighth NMOS transistors. 
   
     
     
         16 . The method of  claim 15 , wherein the receiving the first to the fourth input signals, the first and the second selection signals, and the first and the second complementary signals comprises:
 providing the second selection signal to ninth PMOS transistor connected to a source via the first and the fifth PMOS transistors and via the second and the seventh PMOS transistors;   providing the second complementary selection signal to tenth PMOS transistor connected to the source via the third and the sixth PMOS transistors and via the fourth and the eighth transistors;   providing the second complementary selection signal to ninth NMOS transistor connected to a ground via the first and the fifth NMOS transistors and via the second and the seventh NMOS transistors; and   providing the second selection signal to tenth NMOS transistor connected to the ground via the third and the sixth NMOS transistors and via the fourth and the eighth NMOS transistors, wherein
 the second selection signal and the second complementary selection signal are only provided to a circuit including the ninth and tenth PMOS transistors and the ninth and the tenth NMOS transistors. 
   
     
     
         17 . The method of  claim 16 , wherein the ninth and the tenth PMOS transistors, and the ninth and the tenth NMOS transistors are commonly connected at an internal node, and wherein the transmitting one of the first to the fourth input signals to the output comprises:
 generate an output signal at the output by inverting an internal signal of the internal node.   
     
     
         18 . A four input multiplexer integrated circuit (MXT4) associated with an integrated circuit (IC), the MXT4 comprising:
 a complementary signal generator circuit configured to receive first and second selection signals, and to generate first and second complementary selection signals by inverting the first and the second selection signals, respectively; and   first to fourth PMOS stacks configured to receive first to fourth input signals, respectively, and to receive one of the first selection signal and the first complementary selection signal;   first to fourth NMOS stacks configured to receive the first to fourth input signals, respectively, and to receive one of the first selection signal and the first complementary selection signal;   a first PMOS and NMOS stack and a second PMOS and NMOS stack, the first PMOS and NMOS stack and the second PMOS and NMOS stock each configured to receive the second selection signal and the second complementary selection signal; and   an inverter configured to receive an internal signal from the first stack and the second stack, and to generate an output signal at an output.   
     
     
         19 . The MXT4 of  claim 18 , wherein
 the first PMOS stack and the second PMOS stack are connected in parallel between a source and a first node,   the third PMOS stack and the fourth PMOS stack are connected in parallel between the source and a second node,   the first NMOS stack and the second NMOS stack are connected in parallel between a ground and a third node, and   the third NMOS stack and the fourth NMOS stack are connected in parallel between the ground and a fourth node.   
     
     
         20 . The MXT4 of  claim 19 , wherein
 the first PMOS and NMOS stack is connected between the first node and the third node, and   the second PMOS and NMOS stack is connected between the second node and the fourth node.