Semiconductor device comprising counter-doped regions

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate with a well region and a drift region in the semiconductor substrate; one or more counter-doped regions in the drift region, the plurality of counter-doped regions being directly below the second insulating structure and aligned along a direction vertical to a surface of the semiconductor substrate to divide the drift region into a plurality of parts and the plurality of counter-doped regions in the drift region being separated by the drift region. The semiconductor device further includes a gate structure on the semiconductor substrate, the gate structure covering a portion of the well region and a portion of the drift region; and a source electrode in the well region on one side of the gate structure and a drain electrode in the drift region on another side of the gate structure.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor substrate with a well region and a drift region in the semiconductor substrate;   one or more counter-doped regions in the drift region, the plurality of counter-doped regions being directly below the second insulating structure and aligned along a direction vertical to a surface of the semiconductor substrate to divide the drift region into a plurality of parts and the plurality of counter-doped regions in the drift region being separated by the drift region, wherein the edge of the drift region facing the well region and the edge of each of the plurality of counter-doped regions facing the well region are leveled with each other and perpendicular to the surface of the semiconductor substrate;   a gate structure on the semiconductor substrate, the gate structure covering a portion of the well region and a portion of the drift region; and   a source electrode in the well region on one side of the gate structure and a drain electrode in the drift region on another side of the gate structure.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein:
 boundaries of the one or more counter-doped regions facing the well region level with a boundary of the drift region or exceed the boundary of the drift region; and   after forming more than one of the one or more counter-doped regions, each counter-doped region is separated from another counter-doped region by a certain distance.   
     
     
         3 . The semiconductor device according to  claim 1 , further including:
 a first insulating structure in the well region and a second insulating structure in the drift region.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein:
 the one or more counter-doped regions are formed under the second insulating structure in the drift region.   
     
     
         5 . The semiconductor device according to  claim 3 , wherein:
 the source electrode is formed between the gate structure and the first insulating structure; and   the drain electrode is formed on a side of the second insulating structure that is facing away from the gate structure.   
     
     
         6 . The semiconductor device according to  claim 1 , further including:
 a body-tie electrode in the well region, the body-tie electrode located on a side of the first insulating structure that is facing away from the source electrode.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein:
 the semiconductor device is N-type, the well region, the body-tie region, and the one or more counter-doped regions being doped with P-type dopants, and the drift region, the source electrode, and the drain electrode being doped with N-type dopants; or   the semiconductor device is P-type, the well region, the body-tie region, and the counter-doped regions being doped with N-type dopants, and the drift region, the source electrode, and the drain electrode being doped with P-type dopants.   
     
     
         8 . The semiconductor device according to  claim 3 , wherein:
 the source electrode is on the one side of the gate structure between the first insulation structure and the gate structure, and   the drain electrode is on the another side of the second insulation structure away from the gate structure   
     
     
         9 . The semiconductor device according to  claim 1 , wherein:
 in the plurality of counter-doped regions, each counter-doped region is separated from another counter-doped region by a certain distance in the drift region.   
     
     
         10 . The semiconductor device according to  claim 1 , wherein:
 the plurality of counter-doped regions have different doping depths, and   doping concentrations of the ions doped in the plurality of counter-doped regions decrease as the doping depth increase.