Systems and Methods for Compiler Guided Secure Resource Sharing

Abstract

A data processing system is disclosed that includes an Input/output (I/O) interface to receive incoming data and an in-line accelerator coupled to the I/O interface. The in-line accelerator is configured to receive the incoming data from the I/O interface and to automatically remove all timing channels that potentially form through any shared resources. A generic technique of the present design avoids timing channels between different types of resources. A compiler is enabled to automatically apply this generic pattern to secure shared resources.

1 . A computer-readable storage medium on which is stored one or more sets of instructions embodying a computer-implemented method comprising:
 analyzing, with a compiler, performance and area objectives of different designs including a spatial isolation design having spatially isolated resources for each user, a shared design having shared resources for each user, and a hybrid design; and   generating a single utility function for each design based on area and performance objectives for each design.   
     
     
         2 . The computer-readable storage medium of  claim 1 , the computer-implemented method further comprising:
 creating a performance area model based on the utility functions.   
     
     
         3 . The computer-readable storage medium of  claim 2 , the computer-implemented method further comprising:
 selecting a Pareto-optimal choice among the different designs based on the performance area model.   
     
     
         4 . The computer-readable storage medium of  claim 3 , wherein the performance area model reduces a number of synthesis runs required for full design space exploration. 
     
     
         5 . The computer-readable storage medium of  claim 1 , wherein for a spatial isolation design having N number of bidders, a utility function is based on area, effective latency, and user-specified weightage associated with the area and the effective latency for the spatial isolation design. 
     
     
         6 . The computer-readable storage medium of  claim 5 , wherein the area increases linearly and performance does not change as a number of bidders increases for the spatial isolation design. 
     
     
         7 . The computer-readable storage medium of  claim 1 , wherein for the shared design having N number of bidders, an area of an inserted arbiter increases and latency increases as a number of bidders increases. 
     
     
         8 . The computer-readable storage medium of  claim 1 , wherein the hybrid design includes k groups among N number of bidders with each k group sharing a resource. 
     
     
         9 . A computer-implemented method comprising:
 analyzing, with a compiler, performance and area objectives of different designs including spatial isolation having spatially isolated resources for each user, a shared design having shared resources for each user, and a hybrid design; and   generating a single utility function for each design based on area and performance objectives for each design.   
     
     
         10 . The computer-implemented method of  claim 9 , further comprising:
 creating a performance area model based on the utility functions.   
     
     
         11 . The computer-implemented method of  claim 10 , further comprising:
 selecting a Pareto-optimal choice among the different designs based on the performance area model.   
     
     
         12 . The computer-implemented method of  claim 11 , wherein the performance area model reduces a number of synthesis runs required for full design space exploration. 
     
     
         13 . The computer-implemented method of  claim 9 , wherein for a spatial isolation design having N number of bidders, a utility function is based on area, effective latency, and user-specified weightage associated with the area and the effective latency for the spatial isolation design. 
     
     
         14 . The computer-implemented method of  claim 13 , wherein the area increases linearly and performance does not change as a number of bidders increases. 
     
     
         15 . The computer-implemented method of  claim 9 , wherein for the shared design having N number of bidders, an area of an inserted arbiter increases and latency increases as a number of bidders increases. 
     
     
         16 . The computer-implemented method of  claim 9 , wherein the hybrid design includes k groups among N number of bidders with each k group sharing a resource. 
     
     
         17 . A data processing system comprising:
 a computer-readable storage medium to store instructions; and   a processor coupled to the computer-readable storage medium, the processor is configured to analyze performance and area objectives of different designs including spatial isolation having spatially isolated resources for each user, a shared design having shared resources for each user, and a hybrid design and to generate a single utility function for each design based on area and performance objectives for each design.   
     
     
         18 . The data processing system of  claim 17 , the processor is further configured to create a performance area model based on the utility functions. 
     
     
         19 . The data processing system of  claim 18 , the processor is further configured to select a Pareto-optimal choice among the different designs based on the performance area model. 
     
     
         20 . The data processing system of  claim 17 , wherein for a spatial isolation design having N number of bidders, a utility function is based on area, effective latency, and user-specified weightage associated with the area and the effective latency for the spatial isolation design.