Methods and systems to improve printed electrical components and for integration in circuits

Abstract

Methods and systems to improve printed electrical components and for integration in circuits are disclosed. Passive components, e.g., capacitors, resistors and inductors, can be printed directly into a solid ceramic block using additive manufacturing. A grounded conductive plane or a conductive cage may be placed between adjacent electrical components, or around each component, to minimize unwanted parasitic effects in the circuits, such as, e.g., parasitic capacitance or parasitic inductance. Resistors may be printed in non-traditional shapes, for example, S-shape, smooth S-shape, U-shape, V-shape, Z-shape, zigzag-shape, and any other acceptable alternative configurations. The flexibility in shapes and sizes of the printed resistors allows optimal space usage of the ceramic block. The present invention also discloses an electrical component comprising combined predetermined values of capacitance, resistance and inductance. The integration and adjustability of a multi-property device can provide significant advantages in electronics manufacturing.

What is claimed is: 
     
         1 - 20 . (canceled) 
     
     
         21 . A system, comprising:
 a ceramic matrix packaging comprising an embedded resistor, an embedded capacitor, an embedded inductor, or an embedded multi-property device, or any combination thereof, disposed within the ceramic matrix packaging.   
     
     
         22 . The system of  claim 21 , further comprising:
 wherein the embedded resistor, embedded capacitor, embedded inductor, or embedded multi-property device, or any combination thereof, is oriented at an angle to minimize a parasitic effect.   
     
     
         23 . The system of  claim 21 , further comprising:
 wherein the embedded resistor, embedded capacitor, embedded inductor, or embedded multi-property device, or any combination thereof, is oriented at an angle to optimize space usage of the ceramic matrix.   
     
     
         24 . The system of  claim 21 , further comprising:
 wherein the multi-property device comprises a helical coil encased in a cylindrical housing, and   wherein the cylindrical housing comprises barium titanate.   
     
     
         25 . The system of  claim 24 , further comprising:
 wherein the multi-property device comprises four electrodes, and   wherein inductance-capacitance properties is based on electrode pairs.   
     
     
         26 . The system of  claim 21 , further comprising:
 wherein capacitance, resistance, and inductance of the multi-property device are adjustable based on at least one of an intermediate shape and an intermediate ink.   
     
     
         27 . The system of  claim 21 , further comprising:
 wherein the resistor comprises a Z-shape, a U-shape, a S-shape, a smooth S-shape, or a crescent-shape.   
     
     
         28 . The system of  claim 21 , further comprising:
 wherein the inductor comprises a helical coil, and   wherein the inductor does not comprise a core.   
     
     
         29 . The system of  claim 21 , further comprising:
 wherein the ceramic matrix packaging comprises at least one air gap disposed between a pair of the embedded resistor, embedded capacitor, embedded inductor, or embedded multi-property device, or any combination thereof.   
     
     
         30 . The system of  claim 21 , further comprising:
 wherein formation of the integrated circuit is specified by successive additions of a plurality of voxels of material.   
     
     
         31 . The system of  claim 21 , further comprising:
 wherein the embedded resistor, embedded capacitor, embedded inductor, or embedded multi-property device, or any combination thereof, is sintered to the ceramic matrix packaging.   
     
     
         32 . An system, comprising:
 a ceramic matrix packaging;   a circuit board,   wherein the ceramic matrix packaging comprises an embedded resistor, capacitor, inductor, or multi-property device, or any combination thereof, disposed within the ceramic matrix packaging; and   a conductive cage encapsulating the embedded resistor, capacitor, inductor, or multi-property device, or any combination thereof.   
     
     
         33 . The system of  claim 32 , further comprising:
 wherein the conductive cage comprises a general shape of the embedded resistor, capacitor, inductor, or multi-property device, or any combination thereof, to which it encapsulates.   
     
     
         34 . The system of  claim 32 , further comprising:
 wherein the conductive cage is larger in size than the embedded resistor, capacitor, inductor, or multi-property device, or any combination thereof, to which it encapsulates.   
     
     
         35 . The system of  claim 32 , further comprising:
 wherein the conductive cage is one voxel thick.   
     
     
         36 . The system of  claim 32 , further comprising:
 wherein a distance between a pair of the embedded resistor, capacitor, inductor, or multi-property device, or any combination thereof, is less than 10 microns.   
     
     
         37 . The system of  claim 32 , further comprising:
 wherein the conductive cage comprises two openings, and   wherein the openings are larger in diameter than electrodes of the embedded resistor, capacitor, inductor, or multi-property device, or any combination thereof.   
     
     
         38 . The system of  claim 32 , further comprising:
 wherein the conductive cage is grounded to the lid or a circuit board.   
     
     
         39 . A system, comprising:
 a ceramic matrix packaging,   wherein the ceramic matrix packaging comprises an embedded resistor, capacitor, inductor, or multi-property device, or any combination thereof disposed within the ceramic matrix packaging; and   a conductive plane disposed between the embedded resistor, capacitor, inductor, or multi-property device, or any combination thereof, to shield magnetic flux.   
     
     
         40 . The system of  claim 39 , further comprising:
 wherein the conductive plane is grounded to the lid or the circuit board.