Methods and apparatuses to form self-aligned caps

Abstract

At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

1 . (canceled) 
     
     
         2 . An apparatus, comprising:
 a substrate;   a dielectric layer over the substrate;   at least one trench in the dielectric layer, the trench having dielectric sidewalls;   a conductive material in the at least one trench, the conductive material comprising copper and cobalt, and the conductive material comprising an uppermost surface having an exposed portion; and   a capping region on the conductive material and on portions of the dielectric sidewalls above the conductive material, wherein the capping region comprises a first rounded corner portion facing the exposed portion of the uppermost surface of the conductive material to provide a first gap laterally between the dielectric layer and the capping region, and wherein the capping region comprises a second rounded corner portion at an upper surface of the capping region to provide a second gap laterally between the dielectric layer and the capping region, the second gap over the first gap, and wherein a contact region between the dielectric layer and the capping region is less than a vertical thickness of the capping region to provide a vertical height of direct contact between the dielectric layer and the capping region that is less than the vertical thickness of the capping region.   
     
     
         3 . The apparatus of  claim 2 , wherein a top of the capping region near the dielectric layer is no higher than a top boundary of the dielectric layer that is near the capping region. 
     
     
         4 . The apparatus of  claim 2 , wherein the conductive material is no higher than a top boundary of the dielectric layer at a location near to the conductive material. 
     
     
         5 . The apparatus of  claim 2 , further comprising
 a barrier layer between the conductive material and the dielectric sidewalls of the at least one trench.   
     
     
         6 . The apparatus of  claim 2 , wherein the capping region comprises cobalt. 
     
     
         7 . The apparatus of  claim 2 , wherein the dielectric layer comprises a low-k material. 
     
     
         8 . The apparatus of  claim 2 , wherein the dielectric layer comprises silicon, oxygen, and carbon. 
     
     
         9 . The apparatus of  claim 2 , wherein the substrate comprises a semiconductor material. 
     
     
         10 . The apparatus of  claim 2 , wherein the conductive material is a part of an interconnect. 
     
     
         11 . The apparatus of  claim 2 , wherein the dielectric layer comprises carbon doped silicon oxide. 
     
     
         12 . A data processing system comprising:
 a memory;   a processor coupled to the memory, the processor comprising:
 a substrate; 
 a dielectric layer over the substrate; 
 at least one trench in the dielectric layer, the trench having dielectric sidewalls; 
 a conductive material in the at least one trench, the conductive material comprising copper and cobalt, and the conductive material comprising an uppermost surface having an exposed portion; and 
 a capping region on the conductive material and on portions of the dielectric sidewalls above the conductive material, wherein the capping region comprises a first rounded corner portion facing the exposed portion of the dielectric layer and the capping region, and wherein the capping region comprises a second rounded corner portion at an upper surface of the capping region to provide a second gap laterally between the dielectric layer and the capping region, the second gap over the first gap, and wherein a contact region between the dielectric layer and the capping region is less than a vertical thickness of the capping region to provide a vertical height of direct contact between the dielectric layer and the capping region that is less than the vertical thickness of the capping region. 
   
     
     
         13 . The data processing system of  claim 12 , wherein a top of the capping region near the dielectric layer is no higher than a top boundary of the dielectric layer that is near the capping region. 
     
     
         14 . The data processing system of  claim 12 , wherein the conductive material is no higher than a top boundary of the dielectric layer at a location near to the conductive material. 
     
     
         15 . The data processing system of  claim 12 , wherein the electronic device further comprises a barrier layer between the conductive material and the dielectric sidewalls of the at least one trench. 
     
     
         16 . The data processing system of  claim 12 , wherein the capping region comprises cobalt. 
     
     
         17 . The data processing system of  claim 12 , wherein the dielectric layer comprises a low-k material. 
     
     
         18 . The data processing system of  claim 12 , wherein the dielectric layer comprises silicon, oxygen, and carbon. 
     
     
         19 . The data processing system of  claim 12 , wherein the substrate comprises a semiconductor material. 
     
     
         20 . The data processing system of  claim 12 , wherein the conductive material is a part of an interconnect. 
     
     
         21 . The data processing system of  claim 12 , wherein the dielectric layer comprises carbon doped silicon oxide.