Low-cost packaging for fluidic and device co-integration

Abstract

The present disclosure provides methods for packaging a chip and packaged chips in which the chip and packaging are co-planar and gap-less. In certain instances, the packaged chip has electrodes or fluidics integrated with the chip.

1 .- 105  (canceled) 
     
     
         106 . A packaged chip, comprising:
 (a) a chip having a first surface and a second surface;   (b) a carrier surrounding and bonded to the chip, wherein the first surface of the chip is substantially planar with respect to a surface of the carrier;   (c) global alignment features on the carrier, which global alignment features are aligned to the chip; and   (d) an electrode aligned to the global alignment features and in electrical contact with the chip, wherein the electrode is not wire bonded to the chip and the electrode is in electrical communication with a contact pad on the chip.   
     
     
         107 . The packaged chip of  claim 106 , wherein the global alignment features comprise a dowel or a hole. 
     
     
         108 . The packaged chip of  claim 106 , wherein a gap between the planarizing surface and the first surface of the chip and the carrier is less than about 10 microns (μm). 
     
     
         109 . The packaged chip of  claim 106 , wherein the chip further comprises a local alignment feature. 
     
     
         110 . The packaged chip of  claim 106 , wherein the carrier is bonded to the chip without a gap. 
     
     
         111 . The packaged chip of  claim 106 , wherein the chip comprises an integrated circuit (IC), a light-emitting diode (LED), or a micro-electromechanical system (MEMS). 
     
     
         112 . The packaged chip of  claim 106 , wherein the chip is not attached to a printed circuit board. 
     
     
         113 . The packaged chip of  claim 106 , further comprising a fluidic cap attached to the carrier and aligned to the global alignment features. 
     
     
         114 . The packaged chip of  claim 113 , wherein the fluidic cap comprises a dowel, the carrier comprises a hole, and the dowel is fit into the hole to align the fluidic cap to the carrier. 
     
     
         115 . The packaged chip of  claim 113 , wherein the fluidic cap comprises a hole, the carrier comprises a dowel, and the dowel is fit into the hole to align the fluidic cap to the carrier. 
     
     
         116 . The packaged chip of  claim 113 , wherein the fluidic cap comprises a first hole, the carrier comprises a second hole, and a dowel is fit into the first hole and the second hole to align the fluidic cap to the carrier. 
     
     
         117 . The packaged chip of  claim 113 , further comprising a first fiducial mark on the fluidic cap that is aligned to a second fiducial mark on the carrier or the chip. 
     
     
         118 . The packaged chip of  claim 113 , wherein the fluidic cap comprises a microfluidic channel, a mixer or a droplet generator. 
     
     
         119 . The packaged chip of  claim 113 , wherein the fluidic cap is attached to the carrier by at least partially melting or dissolving the fluidic cap or the carrier. 
     
     
         120 . The packaged chip of  claim 106 , further comprising a first fiducial mark on a shadow mask that is aligned to a second fiducial mark on the carrier or the chip. 
     
     
         121 . The packaged chip of  claim 106 , wherein an additional chip is aligned to the global alignment features on the carrier. 
     
     
         122 . A method for packaging a chip, the method comprising:
 (a) placing a chip and a carrier on a planarizing surface, wherein the chip comprises a first surface having an electrode therein and a second surface, wherein the chip is placed face down against the planarizing surface such that the first surface is adjacent to the planarizing surface, and wherein the carrier surrounds the chip with a gap between the carrier and the chip;   (b) closing the gap to bond the carrier and side surfaces between the first surface and the second surface of the chip, thereby producing a chip-in-carrier (CiC); and   (c) depositing an electrode on the CiC that electrically addresses the chip, wherein the electrode is deposited through a shadow mask which is aligned to the CiC with an accuracy of from about 10 microns (μm) to about 100 μm.   
     
     
         123 . The method of  claim 122 , wherein the shadow mask comprises a dowel, the CiC comprises a hole, and the dowel is fit into the hole to align the shadow mask with the CiC. 
     
     
         124 . The method of  claim 122 , wherein the shadow mask comprises a hole, the CiC comprises a dowel, and the dowel is fit into the hole to align the shadow mask with the CiC. 
     
     
         125 . The method of  claim 122 , wherein the shadow mask is aligned with the CiC to an accuracy of less than about 10 μm.