US2020334181A1PendingUtilityA1

Data transmission method and data transmission system

56
Assignee: KINETIC TECHPriority: Oct 11, 2017Filed: Jul 1, 2020Published: Oct 22, 2020
Est. expiryOct 11, 2037(~11.3 yrs left)· nominal 20-yr term from priority
G06F 2213/0042G06F 13/20G06F 13/4282H04L 25/0272H04L 25/4908H04Q 11/08
56
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

USB transmission and reception devices are provided. A USB transmission device comprises a first interface to receive display port (DP) data via N lanes at a first link rate, wherein N is an integer greater than 1; and a switching re-timer including a plurality of de-serializer circuits to de-serialize the received DP data, a plurality of decoder circuits to decode the de-serialized DP data, a plurality of multiplexer circuits to multiplex the decoded de-serialized DP data received via each of the N lanes into 1/M lanes, wherein M is an integer greater than 1, a plurality of encoder circuits to encode the multiplexed DP data, and a plurality of serializer circuits to serialize the encoded multiplexed DP data and output the serialized multiplexed DP data on each of the N/M lanes at a second link rate, the second link rate being equal to the first link rate multiplied by M.

Claims

exact text as granted — not AI-modified
1 . A universal serial bus (USB) transmission device, comprising:
 a first interface configured to receive display port (DP) data via N lanes at a first link rate, wherein N is an integer greater than 1; and   a switching re-timer including
 a plurality of de-serializer circuits configured to de-serialize the received DP data, 
 a plurality of decoder circuits configured to decode the de-serialized DP data, 
 a plurality of multiplexer circuits configured to multiplex the decoded de-serialized DP data received via each of the N lanes into 1/M lanes, wherein M is an integer greater than 1, 
 a plurality of encoder circuits configured to encode the multiplexed DP data, and 
 a plurality of serializer circuits configured to serialize the encoded multiplexed DP data and output the serialized multiplexed DP data on each of the N/M lanes at a second link rate, wherein the second link rate is equal to the first link rate multiplied by M. 
   
     
     
         2 . The USB transmission device of  claim 1 , wherein:
 the USB transmission device is USB Type-C compliant transmission device.   
     
     
         3 . The USB transmission device of  claim 2 , wherein:
 the USB transmission device is configured to operate in DP Alt Node.   
     
     
         4 . The USB transmission device of  claim 1 , wherein the switching re-timer is configured to:
 receive USB super speed (SS) data via Y lanes at a third link rate; and   output the USB SS data via Z lanes at the third link rate, wherein Y is equal to Z.   
     
     
         5 . The USB transmission device of  claim 4 , wherein:
 the M lanes via which the DP data is output and the Z lanes via which the USB SS data is output are output to main link lines of a USB Type-C connector.   
     
     
         6 . The USB transmission device of  claim 1 , wherein:
 the USB transmission device is a USB Type-C connector.   
     
     
         7 . The USB transmission device of  claim 6 , further comprising:
 four pairs of high-speed differential signal pins.   
     
     
         8 . The USB transmission device of  claim 7 , wherein:
 M equals 2, and   the switching re-timer is configured to output the multiplexed data on each of the M lanes via 2 pairs of the high-speed differential signal pins.   
     
     
         9 . The USB transmission device of  claim 8 , wherein the switching re-timer is configured to:
 receive USB super speed (SS) data via 2 lanes at a third link rate; and   output the USB SS data via 2 lanes at the third link rate over another two pairs of the high-speed differential signal pins.   
     
     
         10 . The USB transmission device of  claim 1 , wherein:
 N equals 4, and   M equals 2.   
     
     
         11 . The USB transmission device of  claim 10 , wherein:
 the switching re-timer is configured to recover a link symbol clock from a clock-to-data recovery circuit.   
     
     
         12 . The USB transmission device of  claim 11 , wherein:
 the switching re-timer is configured to double a speed of the link symbol clock to output the multiplexed data on each of the M lanes at the second link rate.   
     
     
         13 . A universal serial bus (USB) reception device, comprising:
 a first interface configured to receive display port (DP) data via N/M lanes at a first link rate, wherein M is an integer greater than 1, and wherein N is an integer greater than 1;   a switching re-timer including
 a plurality of de-serializer circuits configured to de-serialize the received DP data, 
 a plurality of decoder circuits configured to decode the de-serialized DP data, 
 a plurality of de-multiplexer circuits configured to demultiplex the decoded de-serialized DP data received via each of the N/M lanes into N lanes, 
 a plurality of encoder circuits configured to encode the demultiplexed DP data, and 
 a plurality of serializer circuits configured to serialize the encoded demultiplexed DP data and output the serialized demultiplexed DP data on each of the N lanes at a second link rate, wherein the second link rate is equal to the first link rate divided by M. 
   
     
     
         14 . The USB reception device of  claim 13 , wherein:
 the USB reception device is USB Type-C compliant reception device.   
     
     
         15 . The USB reception device of  claim 14 , wherein:
 the USB reception device is configured to operate in DP Alt Node.   
     
     
         16 . The USB reception device of  claim 13 , wherein the switching re-timer is configured to:
 receive USB super speed (SS) data via Y lanes at a third link rate; and   output the USB SS data via Z lanes at the third link rate, wherein Y is equal to Z.   
     
     
         17 . The USB reception device of  claim 16 , wherein:
 the N lanes via which the DP data is received and the Y lanes via which the USB SS data is received correspond to main link lines of a USB Type-C connector.   
     
     
         18 . The USB reception device of  claim 13 , wherein:
 the USB reception device is a USB Type-C connector.   
     
     
         19 . The USB reception device of  claim 18 , further comprising:
 four pairs of high-speed differential signal pins.   
     
     
         20 . The USB reception device of  claim 19 , wherein:
 N equals 2, and   the switching re-timer is configured to receive the DP data on each of the N lanes via 2 pairs of the high-speed differential signal pins.   
     
     
         21 . The USB reception device of  claim 20 , wherein the switching re-timer is configured to:
 receive USB super speed (SS) data over another two pairs of the high-speed differential signal pins.   
     
     
         22 . The USB reception device of  claim 13 , wherein:
 N equals 2, and   M equals 4.   
     
     
         23 . The USB reception device of  claim 22 , wherein:
 the switching re-timer is configured to recover a link symbol clock from a clock-to-data recovery circuit.   
     
     
         24 . The USB reception device of  claim 23 , wherein:
 the switching re-timer is configured to reduce a speed of the link symbol clock in half to output the demultiplexed data on each of the M lanes at the second link rate.   
     
     
         25 . A data transmission system comprising:
 a universal serial bus (USB) transmission device, comprising:   a first interface configured to receive display port (DP) data via N lanes at a first link rate, wherein N is an integer greater than 1;   a first switching re-timer including
 a plurality of first de-serializer circuits configured to de-serialize the received DP data, 
 a plurality of first decoder circuits configured to decode the de-serialized DP data, 
 a plurality of multiplexer circuits configured to multiplex the decoded de-serialized DP data received via each of the N lanes into 1/M lanes, wherein M is an integer greater than 1, 
 a plurality of first encoder circuits configured to encode the multiplexed DP data, and 
 a plurality of first serializer circuits configured to serialize the encoded multiplexed DP data and output the serialized multiplexed DP data on each of the N/M lanes at a second link rate, wherein the second link rate is equal to the first link rate multiplied by M; and 
   a USB reception device, comprising:   a second interface configured to receive the DP data output from the USB transmission device on N/M lanes at the second link rate;   a second switching re-timer including
 a plurality of second de-serializer circuits configured to de-serialize the received DP data, 
 a plurality of second decoder circuits configured to decode the de-serialized DP data, 
 a plurality of de-multiplexer circuits configured to demultiplex the decoded de-serialized DP data received via each of the N/M lanes into N lanes, 
 a plurality of second encoder circuits configured to encode the demultiplexed DP data, and 
 a plurality of second serializer circuits configured to serialize the encoded demultiplexed DP data and output the serialized demultiplexed DP data on each of the N lanes at the first link rate.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.