Methods Of Manufacturing A Deep Trench Super Junction MOSFET

Abstract

Methods for manufacturing a MOSFET device for high voltage application are disclosed to solve less-than-90-degree trench angle problem. In one embodiment, the trenches in a MOSFET device are filled with different concentrations of P− epitaxial material at different stages to improve charge balance. In an alternative embodiment, several N− epitaxial layers with different concentrations are created before etching trenches filled with P− epitaxial material. Yet in another embodiment, a reverse deep trench process creates a P− epitaxial layer first, and etches trenches to be filled with N− epitaxial and act as active region during device operation, leaving the remaining P− epitaxial columns as non-active regions. The final device structure of the remaining P− epitaxial columns is similar to the traditional P− epitaxial trenches.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor MOS device, comprising:
 forming a N+ substrate layer;   forming a P− epitaxial layer immediately above the N+ substrate layer;   etching a first vertical trench, used as an active region of the device, in the middle of the P− epitaxial layer from its top surface and down to the top surface of the N+ substrate layer, wherein the active region is a region through which a current flows during the device's on-state;   etching a second vertical trench on left side of the first vertical trench, from top surface of the P− epitaxial layer and down to the top surface of the N+ substrate layer, resulting in a first narrow column of a P− epitaxial material between the first vertical trench and the second vertical trench, and having a column width of 5 um or smaller;   etching a third vertical trench on the right side of the first vertical trench, from top surface of the P− epitaxial layer and down to the top surface of N+ substrate layer, resulting in a second narrow column of the P− epitaxial material between the first vertical trench and the third vertical trench, and having a column width of 5 um or smaller; and   filling the first, second and third etched trenches with N− type epitaxial semiconductor material which has lower concentration than that of the N+ substrate layer;   wherein the first and second narrow P− columns are non-active regions as isolation without current flow during the device's operation.   
     
     
         2 . The method of  claim 1 , wherein etching the first vertical trench and the second vertical trench resulting in the first narrow P− column having a uniform width from its top to its bottom. 
     
     
         3 . The method of  claim 2 , wherein the first narrow P− column is perpendicular to the top surface of the N+ substrate. 
     
     
         4 . The method of  claim 1 , wherein the width of the first vertical trench of N− type semiconductor material is wider than the width of either of the first or second narrow P− column. 
     
     
         5 . The method of  claim 1 , wherein the width of the first narrow P− column is equal to the width of the second narrow P− column. 
     
     
         6 . The method of  claim 5 , the ratio of the width of the first vertical trench to the width of either the first or second narrow P− column is maintained at a fixed value during the manufacturing process of the device. 
     
     
         7 . The method of  claim 1 , depositing a first P+ region on top of the first narrow P− column, where the P+ region has higher doping concentration than that of the first narrow P− column. 
     
     
         8 . The method of  claim 7 , forming a N+ diffusion area inside the first P+ region which is used as the source of the MOS device.