Virtualizing interrupt prioritization and delivery

Abstract

Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

1 .- 15 . (canceled) 
     
     
         16 . A processor comprising:
 an instruction decoder to decode a virtual machine (VM) entry instruction; and   an execution unit to execute the decoded VM entry instruction, wherein execution of the decoded VM entry instruction includes virtualization of a processor-priority register (PPR) including storing a maximum of a virtual task-priority register (VTPR) and a servicing virtual interrupt (SVI) value in a virtual PPR.