Systems and methods for implementing core-level predication within a machine perception and dense algorithm integrated circuit

Abstract

Systems and methods for implementing an integrated circuit with core-level predication includes: a plurality of processing cores of an integrated circuit, wherein each of the plurality of cores includes: a predicate stack defined by a plurality of single-bit registers that operate together based on one or more of logical connections and physical connections of the plurality of single-bit registers, wherein: the predicate stack of each of the plurality of processing cores includes a top of stack single-bit register of the plurality of single-bit registers having a bit entry value that controls whether select instructions to the given processing core of the plurality of processing cores is executed.

What is claimed is: 
     
         1 . A system for implementing an integrated circuit with core-level predication, the system comprising:
 a plurality of processing cores of an integrated circuit, wherein each of the plurality of cores includes:
 a predicate stack defined by a plurality of single-bit registers that operate together based on one or more of logical connections and one or more physical connections of the plurality of single-bit registers, 
 wherein:
 the predicate stack of each of the plurality of processing cores includes a top of stack single-bit register of the plurality of single-bit registers having a bit entry value that controls whether select instructions to the given processing core of the plurality of processing cores are executed. 
 
   
     
     
         2 . A method for implementing an integrated circuit with core-level predication, the method comprising:
 implementing a plurality of processing cores of an integrated circuit, wherein each of the plurality of cores includes:
 a predicate stack defined by a plurality of single-bit registers that operate together based on one or more of logical connections and one or more physical connections of the plurality of single-bit registers, 
 wherein:
 the predicate stack of each of the plurality of processing cores includes a top of stack single-bit register of the plurality of single-bit registers having a bit entry value that controls whether select instructions to the given processing core of the plurality of processing cores are executed.