Source/drain contacts for non-planar transistors

Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

What is claimed is: 
     
         1 . A microelectronic device, comprising:
 a substrate   a fin comprising a portion of the substrate;   a transistor on the fin comprising a pair of gate spacers, a gate dielectric layer between the pair of gate spacers and contacting the fin, a gate electrode between the pair of gate spacers and adjacent the gate dielectric, and a capping dielectric layer between the pair of gate spacer and adjacent the gate electrode;   a dielectric material on the substrate, the fin, and the transistor;   a source region in the fin portion of the substrate on one side of the transistor;   a drain region in the fin portion of the substrate on an opposing side of the transistor; and   a contact extending through the dielectric material, wherein the contact is adjacent one of the source region and the drain region, wherein at least one of the contact comprises a contact interface layer adjacent the one of the source region and the drain region, and a conductive contact material adjacent the contact interface layer, and wherein the contact interface layer abuts at least one of a portion of one gate spacer and at least a portion of the capping structure.   
     
     
         2 . The microelectronic device of  claim 1 , wherein the substrate comprises silicon. 
     
     
         3 . The microelectronic device of  claim 1 , wherein the conductive contact material comprises tungsten. 
     
     
         4 . The microelectronic device of  claim 1 , wherein the contact interface layer comprises titanium. 
     
     
         5 . The microelectronic device of  claim 4 , wherein the contact interface layer comprises substantially pure titanium. 
     
     
         6 . The microelectronic device of  claim 1 , further comprising the interface between the contact interface layer and the one of the source region and the drain region. 
     
     
         7 . The microelectronic device of  claim 6 , wherein the interface comprises titanium and silicon. 
     
     
         8 . The microelectronic device of  claim 1 , wherein the contact interface layer abuts at least the portion of one gate spacer and at least the portion of the capping structure. 
     
     
         9 . A method of fabricating a microelectronic device, comprising:
 forming a substrate;   forming a fin from a portion of the substrate;   forming a transistor on the fin comprising:
 forming a pair of gate spacers, forming a gate dielectric layer between the pair of gate spacers and adjacent the fin; 
 forming a gate electrode between the pair of gate spacers and adjacent the gate dielectric; and 
 forming a capping dielectric layer between the pair of gate spacer and adjacent the gate electrode; 
   forming a source region in the fin portion of the substrate on one side of the transistor;   forming a drain region in the fin portion of the substrate on an opposing side of the transistor;   forming a dielectric material on the substrate and the transistor;   forming a contact opening through the dielectric material to expose a portion of one of the source region and the drain region;   forming contact interface layer adjacent the portion of one of the source region and the drain region, wherein the contact interface layer abuts at least one of a portion of one gate spacer and at least a portion of the capping structure; and   forming a conductive contact material adjacent the contact interface layer.   
     
     
         10 . The method of  claim 9 , wherein forming the substrate comprises forming a substrate comprising silicon. 
     
     
         11 . The method of  claim 9 , wherein forming the conductive contact material comprises forming a conductive contact material comprising tungsten. 
     
     
         12 . The method of  claim 9 , wherein forming the contact interface layer comprises depositing a conformal a contact interface layer. 
     
     
         13 . The method of  claim 9 , wherein forming the contact interface layer comprises forming a contact interface layer comprising titanium. 
     
     
         14 . The method of  claim 13 , wherein forming the contact interface layer comprises forming a substantially pure titanium contact interface layer. 
     
     
         15 . The method of  claim 9 , further comprising forming an interface adjacent the portion of one of the source region and the drain region. 
     
     
         16 . The method of  claim 15 , wherein forming the interface comprises titanium and silicon. 
     
     
         17 . The method of  claim 16 , wherein forming the interface comprises:
 forming the substrate comprising silicon;   forming the contact interface layer comprising titanium, and   heating the substrate and the contact interface layer.   
     
     
         18 . The method of  claim 9 , wherein forming the interface comprises forming the interface to reside substantially only between the contact interface layer and the at least one of the source region and the drain region. 
     
     
         19 . The method of  claim 9 , wherein forming the contact interface layer comprises forming the contact interface layer to abut at least the portion of one gate spacer and at least the portion of the capping structure. 
     
     
         20 . The method of  claim 9 , wherein forming the fin comprises etching the substrate.