Automated circuit generation

Abstract

Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

1 .- 11 . (canceled) 
     
     
         12 . A computer-implemented method of generating a circuit comprising:
 receiving, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component;   selecting, by the at least one software system, a plurality of sub-circuit schematics based on the circuit specification parameters; and   combining, by the at least one software system, the sub-circuit schematics to form a circuit schematic for the at least one functional circuit component.   
     
     
         13 . The method of  claim 12 , wherein the at least one functional circuit component is an analog functional circuit component. 
     
     
         14 . The method of  claim 12 , wherein the sub-circuit schematics comprise analog sub-circuit schematics. 
     
     
         15 . The method of  claim 12 , wherein the sub-circuit schematics comprise predefined analog sub-circuit schematics. 
     
     
         16 . The method of  claim 15 , wherein the selected plurality of sub-circuit schematics are a subset of a second plurality of predefined analog sub-circuit schematics. 
     
     
         17 . The method of  claim 16 , wherein the second plurality of predefined analog sub-circuit schematics correspond to the at least one functional analog circuit component. 
     
     
         18 . The method of  claim 16 , wherein the plurality of sub-circuit schematics include alternative sub-circuit schematics for performing the same function using different circuitry. 
     
     
         19 . The method of  claim 12 , the sub-circuit schematics comprising a plurality of analog pins having different electrical characteristics. 
     
     
         20 . The method of  claim 19 , wherein the different electrical characteristics are different voltage or current operating ranges. 
     
     
         21 . The method of  claim 12 , said sub-circuit schematics comprising a plurality of pins, said combining comprising mapping the pins of the sub-circuit schematics. 
     
     
         22 . The method of  claim 21 , wherein one or more pins of said plurality of pins are analog pins. 
     
     
         23 . The method of  claim 21 , wherein said mapping is based on at least one pin map. 
     
     
         24 . The method of  claim 23 , wherein different pin maps specify connections between the plurality of sub-circuit schematic pins for different combinations of selected sub-circuit schematics. 
     
     
         25 . The method of  claim 23 , wherein the at least one pin map is based on the selected sub-circuit schematics. 
     
     
         26 . The method of  claim 23 , wherein said pin map specifies connections between pins of the sub-circuit schematics. 
     
     
         27 . The method of  claim 23 , wherein said pin map specifies connections between pins of the sub-circuit schematics and inputs or outputs of the circuit schematic. 
     
     
         28 . The method of  claim 23 , wherein connected pins have predetermined compatibility. 
     
     
         29 . The method of  claim 21 , wherein mapping the pins comprises connecting the pins in the circuit schematic. 
     
     
         30 . The method of  claim 21 , wherein the mapping is done automatically by the at least one software system based on a plurality of predefined rules. 
     
     
         31 . The method of  claim 12 , wherein different values for the circuit specification parameters generate different analog circuit schematics having different properties for the at least one functional circuit component. 
     
     
         32 . The method of  claim 12 , wherein different sets of circuit specification parameters for different corresponding functional circuit components have different corresponding sets of predefined sub-circuit schematics. 
     
     
         33 . The method of  claim 32 , wherein different values for different sets of circuit specification parameters select different subsets of predefined sub-circuit schematics from one of a plurality of sets of predefined sub-circuit schematics corresponding to different functional circuit components. 
     
     
         34 . The method of  claim 12 , the plurality of circuit specification parameters comprising one or more of: a parameter specifying a physical property or a parameter specifying an electrical property. 
     
     
         35 . The method of  claim 12 , further comprising generating a netlist specifying the selected sub-circuits. 
     
     
         36 . The method of  claim 35 , wherein the netlist is a verilog file. 
     
     
         37 . The method of  claim 12 , wherein the sub-circuit schematics are combined according to a set of rules associated with the at least one functional circuit component to form the circuit schematic for the at least one functional circuit component. 
     
     
         38 . The method of  claim 12 , wherein different circuit specification parameters corresponding to different functional circuit components are processed using different associated sets of rules for combining different sets of sub-circuit schematics. 
     
     
         39 . The method of  claim 12 , wherein different functional circuit components have a corresponding unique set of predefined sub-circuit schematics. 
     
     
         40 . The method of  claim 39 , wherein each unique set of predefined sub-circuit schematics comprises one or more unique predefined analog sub-circuit schematics only used for the corresponding functional circuit component. 
     
     
         41 . The method of  claim 39 , wherein each unique set of predefined sub-circuit schematics comprises one or more predefined analog sub-circuit schematics used for a plurality of corresponding functional circuit components. 
     
     
         42 . The method of  claim 12 , the circuit specification parameters comprising variables and corresponding values. 
     
     
         43 . The method of  claim 42 , wherein the variables and the values are received as text. 
     
     
         44 . The method of  claim 12 , wherein the circuit specification parameters comprise code specifying properties of the circuit schematic. 
     
     
         45 . The method of  claim 44 , wherein different values of the code select different sub-circuit schematics. 
     
     
         46 . A computer system for generating a circuit comprising:
 one or more processors; and   a non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by the computer system, cause the computer system to perform a method comprising:
 receiving, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component; 
 selecting, by the at least one software system, a plurality of sub-circuit schematics based on the circuit specification parameters; and 
 combining, by the at least one software system, the sub-circuit schematics to form a circuit schematic for the at least one functional circuit component. 
   
     
     
         47 . A non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by a computer system, cause the computer system to:
 receive, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component;   select, by the at least one software system, a plurality of sub-circuit schematics based on the circuit specification parameters; and   combine, by the at least one software system, the sub-circuit schematics to form a circuit schematic for the at least one functional circuit component.   
     
     
         48 . A system for generating a circuit comprising:
 means for receiving, by at least one software system executing on at least one computer, a plurality of circuit specification parameters corresponding to at least one functional circuit component;   means for selecting, by the at least one software system, a plurality of sub-circuit schematics based on the circuit specification parameters; and   means for combining, by the at least one software system, the sub-circuit schematics to form a circuit schematic for the at least one functional circuit component.   
     
     
         49 .- 344 . (canceled)