Solid state drive architectures

Abstract

A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

What is claimed is: 
     
         1 . A solid state drive (SSD) comprising:
 Dynamic Random Access Memory (DRAM) logical flash which stores files in the same way as NAND flash and responds to flash commands, wherein the DRAM logical flash comprises:
 DRAM memory; and 
 a DRAM controller to manage data transfers into and out of the DRAM memory; 
   flash memory;   a master SSD controller; and   an interface to connect the SSD to a host having a Central Processing Unit (CPU) such that the CPU exclusively reads data from, and writes to, the DRAM logical flash, the DRAM logical flash providing principal data storage during operation of the CPU;   the SSD controller to independently determine when to transfer the data from the DRAM logical flash to the flash memory;   wherein the master SSD controller organizes data in the DRAM using a File Access Table (FAT) or New Technology File System (NTFS) in a same way that data is organized in the Flash memory; and   wherein a majority of memory commands are handled by the master SSD controller using DRAM so as to reduce a number of writes to the Flash memory, the master controller is configured to independently determine when data should be transferred between the DRAM and the flash memory to reduce a number of write/erase cycles for the flash memory, the master SSD controller is configured to determine when to move data to or from the DRAM based on factors including lack of use of the data.   
     
     
         2 . The drive of  claim 1 , further comprising an energy storage device storing enough power to move data content stored in the DRAM to the flash memory if external power to the solid state drive is interrupted. 
     
     
         3 . The drive of  claim 1 , further comprising a high speed internal bus operating at a speed of at least 400 megabytes per second, in which the DRAM and the flash memory are separately connected to the high speed internal bus, the flash memory being divided into separate modules, each module controlled by a thread, with each of these threads configured to independently interface with the high speed internal bus. 
     
     
         4 . The drive of  claim 1 , wherein the DRAM is the only memory in the SSD that is directly accessible to the CPU. 
     
     
         5 . The drive of  claim 1 , further comprising multiple independent flash controllers each within a separate flash memory module.