Methods and apparatus for synchronizing communication with a memory controller

Abstract

A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

1 . (canceled) 
     
     
         2 . A memory controller comprising:
 an interface circuit to couple to a first memory device and a second memory device, the interface circuit including a first receiver circuit to receive a first read signal of a first phase from the first memory device and second read signal of a second phase from the second memory device;   a first register to store a first receive state corresponding to the first memory device, the first receive state derived from the first phase; and   a second register to store a second receive state corresponding to the second memory device, the second receive state derived from the second phase.   
     
     
         3 . The memory controller of  claim 2 , wherein the first receive state represents a first offset from a clock signal and the second receive state represents a second offset from the clock signal. 
     
     
         4 . The memory controller of  claim 3 , the interface circuit comprising a delay-locked loop to derive the first offset from and the second offset from the clock signal. 
     
     
         5 . The memory controller of  claim 2 , wherein at least one of the first read signal and the second read signal comprises a strobe signal. 
     
     
         6 . The memory controller of  claim 2 , wherein the interface circuit further includes transmitter circuits for transmitting first write data signals to the first memory device and second write data signals to the second memory device, the first register stores a first transmitting timing state for the first write data signals, and the second register stores a second transmitting timing state for the second write data signals. 
     
     
         7 . A method performed by a memory controller, the method comprising:
 receiving a first timing-reference signal and a first data signal from a first memory device;   deriving first phase information from the first timing-reference signal;   generating a first data-sampling signal from a clock signal based on the first phase information;   sampling the first data signal with the first data-sampling signal;   receiving a second timing-reference signal and a second data signal from a second memory device;   deriving second phase information from the second timing-reference signal;   generating a second data-sampling signal from the clock signal based on the second phase information; and   sampling the second data signal with the second data-sampling signal.   
     
     
         8 . The method of  claim 7 , wherein generating the first data-sampling signal phase aligns the first data-sampling signal with the first data signal responsive to a phase offset between the first timing-reference signal and the clock signal. 
     
     
         9 . The method of  claim 7 , wherein at least one of the first timing-reference signal and the second timing-reference signal transitions irregularly between high and low logic levels. 
     
     
         10 . The method of  claim 9 , wherein the first timing-reference signal is a pseudo-random signal. 
     
     
         11 . The method of  claim 7 , wherein the first timing-reference signal is not a clock signal. 
     
     
         12 . The method of  claim 7 , further comprising maintaining a phase offset between the first data-sampling signal and the clock signal absent the first timing-reference signal. 
     
     
         13 . The method of  claim 12 , further comprising storing a representation of the phase offset in a register. 
     
     
         14 . A memory controller comprising:
 a first lock circuit to phase adjust a first data-sampling signal relative to a clock signal responsive to a first phase-adjust signal;   a first phase detector to receive a first timing-reference signal of a first phase from a first memory device and to provide the first phase-adjust signal responsive to the first phase;   a first receiver to sample a first data signal from the first memory device with the first timing-reference signal;   a second lock circuit to phase adjust a second data-sampling signal relative to the clock signal responsive to a second phase-adjust signal;   a second phase detector to receive a second timing-reference signal of a second phase from a second memory device and to provide the second phase-adjust signal responsive to the second phase; and   a second receiver to sample a second data signal from the second memory device with the second timing-reference signal.   
     
     
         15 . The memory controller of  claim 14 , wherein each of the first timing-reference signal and the second timing-reference signal transitions irregularly between high and low logic levels. 
     
     
         16 . The memory controller of  claim 15 , wherein each of the first timing-reference signal and the second timing-reference signal is a pseudo-random signal. 
     
     
         17 . The memory controller of  claim 14 , further comprising registers to store representations of the first phase and the second phase. 
     
     
         18 . The memory controller of  claim 17 , wherein the registers store the representations absent the clock signal. 
     
     
         19 . The memory controller of  claim 14 , supporting first and second modes, the memory controller establishing a phase offset between the first data-sampling signal and the clock signal responsive to the first timing-reference signal in the first mode and sampling the first data signal with the first data-sampling signal in the second mode. 
     
     
         20 . The memory controller of  claim 19 , wherein the first mode supports a maintenance operation for the memory controller. 
     
     
         21 . The memory controller of  claim 14 , further comprising a transmitter to transmit a third data signal to the first memory device, the third data signal being timed based on the first phase.