Resistive memory device having a conductive barrier layer

Abstract

A memory device is disclosed. The memory device includes a bottom contact and a memory layer connected to the bottom contact. The memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode; and a barrier layer, configured to substantially prevent conduction of ions or vacancies therethrough, wherein the barrier layer has a resistivity less than 1E-4 Ohm-m, where the barrier layer is between one of: A) the top electrode and the top contact, and B) the memory layer and the bottom contact.

What is claimed is: 
     
         1 . A memory device, comprising:
 a bottom contact;   a memory layer connected to the bottom contact, wherein the memory layer comprises a memory layer material having a variable resistivity, and wherein a resistivity of the memory layer material is dependent on a concentration of ions or vacancies in the memory layer material;   a top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure, wherein the heterojunction memory structure is configured such that a memory state of the heterojunction memory structure is dependent on a controllably variable concentration of ions or vacancies in the memory layer material, and such that the memory state of the heterojunction memory structure is controllable by applying an electric field to control the concentration of ions or vacancies in the memory layer material;   a top contact on the top electrode; and   a barrier layer, configured to substantially prevent conduction of ions or vacancies therethrough, wherein the barrier layer has a resistivity less than 1E-4 Ohm-m,   wherein the barrier layer is between one of:
 A) the top electrode and the top contact, and 
 B) the memory layer and the bottom contact. 
   
     
     
         2 . The memory device of  claim 1 , further comprising a template layer contacting the memory layer, wherein a crystalline structure of the memory layer matches a crystalline structure of the template layer, and wherein the template layer is between at least one of:
 A) the memory layer and the bottom contact, and   B) the memory layer and the barrier layer.   
     
     
         3 . The memory device of  claim 2 , wherein a conductivity of the template layer is greater than 10×10 6  S m −1 . 
     
     
         4 . The memory device of  claim 1 , wherein a first contact formed at an interface between the barrier layer and the memory layer is ohmic, and wherein a second contact formed at an interface between the memory layer and the top electrode is ohmic. 
     
     
         5 . The memory device of  claim 1 , further comprising a retention layer between the memory layer and the top electrode. 
     
     
         6 . The memory device of  claim 5 , wherein the resistivity of the retention layer is less than 1×10′ Ohm-m. 
     
     
         7 . The memory device of  claim 1 , further comprising a side barrier layer configured to substantially prevent conduction of ions or vacancies therethrough, wherein the side barrier layer contacts each of the memory layer, the top electrode, and the barrier layer. 
     
     
         8 . A method of manufacturing a memory device, comprising:
 forming a bottom contact;   connecting a memory layer to the bottom contact, wherein the memory layer comprises a memory layer material having a variable resistivity, and wherein a resistivity of the memory layer material is dependent on a concentration of ions or vacancies in the memory layer material;   forming a top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure, wherein the heterojunction memory structure is configured such that a memory state of the heterojunction memory structure is dependent on a controllably variable concentration of ions or vacancies in the memory layer material, and such that the memory state of the heterojunction memory structure is controllable by applying an electric field to control the concentration of ions or vacancies in the memory layer material;   forming a top contact on the top electrode; and   forming a barrier layer, configured to substantially prevent conduction of ions or vacancies therethrough, wherein the barrier layer has a resistivity less than 1E-4 Ohm-m,   wherein the barrier layer is between one of:
 A) the top electrode and the top contact, and 
 B) the memory layer and the bottom contact. 
   
     
     
         9 . The method of  claim 8 , further comprising forming a template layer contacting the memory layer, wherein a crystalline structure of the memory layer matches a crystalline structure of the template layer, and wherein the template layer is between at least one of:
 A) the memory layer and the bottom contact, and   B) the memory layer and the barrier layer.   
     
     
         10 . The method of  claim 9 , wherein a conductivity of the template layer is greater than 10×10 6  S m −1 . 
     
     
         11 . The method of  claim 8 , wherein a first contact formed at an interface between the barrier layer and the memory layer is ohmic, and wherein a second contact formed at an interface between the memory layer and the top electrode is ohmic. 
     
     
         12 . The method of  claim 8 , further comprising forming a retention layer between the memory layer and the top electrode. 
     
     
         13 . The method of  claim 12 , wherein the resistivity of the retention layer is less than 1×10′ Ohm-m. 
     
     
         14 . The method of  claim 12 , further comprising forming a side barrier layer configured to substantially prevent conduction of ions or vacancies therethrough, wherein the side barrier layer contacts each of the memory layer, the top electrode, and the barrier layer. 
     
     
         15 . A method of using a memory device, the memory device comprising: a bottom contact; a memory layer connected to the bottom contact, wherein the memory layer comprises a memory layer material having a variable resistivity, and wherein a resistivity of the memory layer material is dependent on a concentration of ions or vacancies in the memory layer material; a top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure, wherein the heterojunction memory structure is configured such that a memory state of the heterojunction memory structure is dependent on a controllably variable concentration of ions or vacancies in the memory layer material, and such that the memory state of the heterojunction memory structure is controllable by applying an electric field to control the concentration of ions or vacancies in the memory layer material; a top contact on the top electrode; a barrier layer, configured to substantially prevent conduction of ions or vacancies therethrough, wherein the barrier layer has a resistivity less than 1E-4 Ohm-m, and wherein the barrier layer is between one of: A) the top electrode and the top contact, and B) the memory layer and the bottom contact, the method comprising:
 applying a first voltage difference across the bottom contact and the top contact, whereby the electric field is applied to the memory layer, and such that a resistivity state of the memory layer is changed;   applying a second voltage difference across the bottom contact and the top contact;   while the second voltage difference is applied, causing a first current to be conducted through the bottom contact, the memory layer, the top electrode, the top contact, and the barrier layer; and   determining the resistivity state of the memory layer based on the second voltage difference and the first current.   
     
     
         16 . The method of  claim 15 , wherein the memory device further comprises a template layer contacting the memory layer, wherein a crystalline structure of the memory layer matches a crystalline structure of the template layer, and wherein the first current is additionally conducted through the template layer. 
     
     
         17 . The method of  claim 16 , wherein a conductivity of the template layer is greater than 10×10 6  S m −1 . 
     
     
         18 . The method of  claim 15 , wherein the memory device further comprises a retention layer between the memory layer and the top electrode, wherein the retention layer has a variable ionic conductivity, and is configured to selectively resist ionic conduction, and wherein the method further comprises causing the first current to be conducted through the retention layer. 
     
     
         19 . The method of  claim 18 , wherein the resistivity of the retention layer is less than 1×10′ Ohm-m. 
     
     
         20 . The method of  claim 15 , wherein the memory device further comprises a side barrier layer configured to substantially prevent conduction of ions or vacancies therethrough, wherein the side barrier layer contacts each of the memory layer, the top electrode, and the barrier layer, and wherein the method further comprises confining ions of the top electrode and the memory layer to the top electrode and the memory layer with the barrier layer and the side barrier layer.