Dataflow Triggered Tasks for Accelerated Deep Learning

Abstract

Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow based computations on wavelets of data. Each processing element has a compute element and a routing element. Each compute element has memory. Each router enables communication via wavelets with nearest neighbors in a 2D mesh. Routing is controlled by respective virtual channel specifiers in each wavelet and routing configuration information in each router. A compute element receives a particular wavelet comprising a particular virtual channel specifier and a particular data element. Instructions are read from the memory of the compute element based at least in part on the particular virtual channel specifier. The particular data element is used as an input operand to execute at least one of the instructions.

1 . (canceled) 
     
     
         2 . A method comprising:
 sending a packet from a sending processing element to a receiving processing element via a fabric and in accordance with a selected one of a plurality of communication pathways, wherein the packet comprises a first field and a second field, the sending is via a selected one of a plurality of fabric ports of the sending processing element, the sending processing element fabric ports are coupled to the fabric, and the selected communication pathway and the selected fabric port are determined based at least in part on the first field; and   executing an instruction fetched from an address of a memory of the receiving processing element, wherein the address is determined based at least in part on the first field and the executing uses the second field.   
     
     
         3 . The method of  claim 2 , further comprising computing the address as an arithmetic function of the first field and using at least a portion of the second field as an input operand of the fetched instruction. 
     
     
         4 . The method of  claim 3 , wherein the sending is performed at least in part by a router of the sending processing element, the router comprises the plurality of fabric ports, the executing is performed at least in part by a compute element of the receiving processing element, the compute element is enabled to execute a set of programmed instructions, and the fetched instruction is an instance of a member of the set of programmed instructions. 
     
     
         5 . The method of  claim 4 , further comprising:
 maintaining block/unblock state corresponding to each of the communication pathways;   setting the block/unblock state corresponding to at least a first one of the communication pathways to indicate a block state responsive to a block instruction specifying at least the first communication pathway;   setting the block/unblock state corresponding to at least a second one of the communication pathways to indicate an unblock state responsive to an unblock instruction specifying at least the second communication pathway;   selecting the fetched instruction for execution responsive to the block/unblock state of the communication pathway identified by the first field indicating the unblock state;   selecting an instruction other than the fetched instruction for execution responsive to the block/unblock state of the communication pathway identified by the first field indicating the block state; and   wherein the block instruction and the unblock instruction are respective instances of respective members of the set of programmed instructions.   
     
     
         6 . The method of  claim 5 , wherein the packet comprises a third field and the selecting the fetched instruction is further responsive to the third field. 
     
     
         7 . The method of  claim 3 , wherein the executing implements at least a portion of one or more of: computing an activation of a neural network, computing a partial sum of activations of a neural network, computing an error of a neural network, computing a gradient estimate of a neural network, and updating a weight of a neural network. 
     
     
         8 . The method of  claim 3 , wherein the input operand comprises at least a portion of one of: a weight of a neural network, an activation of a neural network, a partial sum of activations of a neural network, an error of a neural network, a gradient estimate of a neural network, and a weight update of a neural network. 
     
     
         9 . The method of  claim 8 , wherein a substantially whole wafer comprises the sending processing element, the receiving processing element, and the fabric. 
     
     
         10 . An apparatus comprising:
 a sending processing element comprising a plurality of fabric ports;   a receiving processing element comprising a memory;   a fabric coupled to the fabric ports;   wherein the sending processing element is enabled to send a packet to the receiving processing element via the fabric and further via a selected one of the fabric ports in accordance with a selected one of a plurality of communication pathways;   wherein the packet comprises a first field and a second field;   wherein the selected communication pathway and the selected fabric port are determined based at least in part on the first field;   wherein the receiving processing element is enabled to execute an instruction fetched from an address of the memory; and   wherein the address is determined based at least in part on the first field and the executing uses the second field.   
     
     
         11 . The apparatus of  claim 10 , wherein the receiving processing element is further enabled to compute the address as an arithmetic function of the first field and to use at least a portion of the second field as an input operand of the fetched instruction. 
     
     
         12 . The apparatus of  claim 11 , wherein the sending processing element further comprises a router comprising the plurality of fabric ports, the receiving processing element further comprises a compute element comprising the memory, the compute element is enabled to execute a set of programmed instructions, and the fetched instruction is an instance of a member of the set of programmed instructions. 
     
     
         13 . The apparatus of  claim 12 , wherein:
 the compute element is further enabled
 to maintain block/unblock state corresponding to each of the communication pathways, 
 to set the block/unblock state corresponding to at least a first one of the communication pathways to indicate a block state responsive to a block instruction specifying at least the first communication pathway, 
 to set the block/unblock state corresponding to at least a second one of the communication pathways to indicate an unblock state responsive to an unblock instruction specifying at least the second communication pathway, 
 to select the fetched instruction for execution responsive to the block/unblock state of the communication pathway identified by the first field indicating the unblock state, and 
 to select an instruction other than the fetched instruction for execution responsive to the block/unblock state of the communication pathway identified by the first field indicating the block state; and 
   wherein the block instruction and the unblock instruction are respective instances of respective members of the set of programmed instructions.   
     
     
         14 . The apparatus of  claim 11 , wherein the executing implements at least a portion of one or more of: computing an activation of a neural network, computing a partial sum of activations of a neural network, computing an error of a neural network, computing a gradient estimate of a neural network, and updating a weight of a neural network. 
     
     
         15 . The apparatus of  claim 11 , wherein the input operand comprises at least a portion of one of: a weight of a neural network, an activation of a neural network, a partial sum of activations of a neural network, an error of a neural network, a gradient estimate of a neural network, and a weight update of a neural network. 
     
     
         16 . The apparatus of  claim 15 , wherein a substantially whole wafer comprises the sending processing element, the receiving processing element, and the fabric. 
     
     
         17 . A system comprising:
 means for sending a packet from a sending processing element to a receiving processing element via a fabric and in accordance with a selected one of a plurality of communication pathways, wherein the packet comprises a first field and a second field, the means for sending is operable via a selected one of a plurality of fabric ports of the sending processing element, the sending processing element fabric ports are coupled to the fabric, and the selected communication pathway and the selected fabric port are determined based at least in part on the first field; and   means for executing an instruction fetched from an address of a memory of the receiving processing element, wherein the address is determined based at least in part on the first field and the means for executing uses the second field.   
     
     
         18 . The system of  claim 17 , further comprising means for computing the address as an arithmetic function of the first field and means for using at least a portion of the second field as an input operand of the fetched instruction. 
     
     
         19 . The system of  claim 18 , wherein the means for sending comprises a router of the sending processing element, the router comprises the plurality of fabric ports, the means for executing comprises a compute element of the receiving processing element, the compute element is enabled to execute a set of programmed instructions, and the fetched instruction is an instance of a member of the set of programmed instructions. 
     
     
         20 . The system of  claim 19 , further comprising:
 means for maintaining block/unblock state corresponding to each of the communication pathways;   means for setting the block/unblock state corresponding to at least a first one of the communication pathways to indicate a block state responsive to a block instruction specifying at least the first communication pathway;   means for setting the block/unblock state corresponding to at least a second one of the communication pathways to indicate an unblock state responsive to an unblock instruction specifying at least the second communication pathway;   means for selecting the fetched instruction for execution responsive to the block/unblock state of the communication pathway identified by the first field indicating the unblock state;   means for selecting an instruction other than the fetched instruction for execution responsive to the block/unblock state of the communication pathway identified by the first field indicating the block state; and   wherein the block instruction and the unblock instruction are respective instances of respective members of the set of programmed instructions.   
     
     
         21 . The system of  claim 18 , wherein execution of the fetched instruction implements at least a portion of one or more of: computing an activation of a neural network, computing a partial sum of activations of a neural network, computing an error of a neural network, computing a gradient estimate of a neural network, and updating a weight of a neural network.