Optimizing power usage by factoring processor architectural events to pmu

Abstract

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

What is claimed is: 
     
         1 . A processor comprising:
 a plurality of cores including a first core of a first core type and a second core of a second core type, wherein the first core and second core are able to operate concurrently at different frequencies in different power states;   a plurality of thermal sensors to provide thermal data, including at least a first thermal sensor to provide first thermal data for the first core and at least a second thermal sensor to provide second thermal data for the second core;   a plurality of counters integral to the first core, each counter to count a number of occurrences of an architectural event, the plurality of counters including a first counter to count a number of instructions retired, a second counter to count last level cache misses, a third counter to count translation lookaside buffer (TLB) misses, and a fourth counter to count branch mispredictions;   a system interconnect coupled to the plurality of cores, the system interconnect able to operate in a plurality of different power states; and   a power controller coupled to the system interconnect, the power controller to control the power states of the first core and the second core in accordance with the thermal data.   
     
     
         2 . The processor of  claim 1  wherein the power controller to control the power states of the interconnect in accordance with the thermal data. 
     
     
         3 . The processor of  claim 2  wherein the power controller is to control the power states of the system interconnect, the first core, and the second core in accordance with a specified power limit. 
     
     
         4 . The processor of  claim 1  wherein the power controller is to attempt to optimize performance within a specified thermal budget. 
     
     
         5 . The processor of  claim 2  wherein the first core is to operate at a first frequency in a first power state, the second core is to operate at a second frequency in a second power state, and the system interconnect is to operate at a third frequency in a third power state. 
     
     
         6 . The processor of  claim 4  further comprising:
 a third thermal sensor in combination with the first thermal sensor to provide the first thermal data for the first core. 
 
     
     
         7 . The processor of  claim 1  further comprising:
 a functional unit coupled to the plurality of cores over the system interconnect; and 
 a cache shared by the plurality of cores. 
 
     
     
         8 . The processor of  claim 7 , further comprising:
 a memory controller coupled to the system interconnect and a system memory device.   
     
     
         9 . The processor of  claim 8 , further comprising:
 a network interface coupled to the system interconnect;   a flash memory coupled to the interconnect; and   a display coupled to the system interconnect.   
     
     
         10 . The processor of  claim 1 , wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on the first thermal data and/or the second thermal data. 
     
     
         11 . The processor of  claim 1  wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on current power states of the plurality of cores and the power limit. 
     
     
         12 . The processor of  claim 1  wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on performance data determined from one or more of the plurality of counters. 
     
     
         13 . The processor of  claim 1  wherein the plurality of counters integral to the first core comprise a first plurality of counters, the processor further comprising: a second plurality of counters integral to the second core, each counter of the second plurality of counters to count a number of occurrences of one of the architectural events, the second plurality of counters including a fifth counter to count a number of instructions retired, a sixth counter to count last level cache misses, a seventh counter to count translation lookaside buffer (TLB) misses, and an eighth counter to count branch mispredictions. 
     
     
         14 . A method comprising:
 operating a plurality of cores at a plurality of different frequencies associated with different power states, the plurality of cores including a first core of a first core type and a second core of a second core type;   providing thermal data from a plurality of thermal sensors, including providing first thermal data from a first thermal sensor associated with the first core and providing second thermal data from a second thermal sensor associated with the second core;   counting, by a plurality of counters integral to the first core, a corresponding number of occurrences of architectural events, the plurality of counters including a first counter to count a number of instructions retired, a second counter to count last level cache misses, a third counter to count translation lookaside buffer (TLB) misses, and a fourth counter to count branch mispredictions;   operating a system interconnect coupled to the plurality of cores in a plurality of different power states; and   controlling, by a power controller coupled to the system interconnect, the power states of the first core and the second core in accordance with the thermal data.   
     
     
         15 . The method of  claim 14  further comprising:
 controlling, by the power controller, the power states of the interconnect in accordance with the thermal data. 
 
     
     
         16 . The method of  claim 15  further comprising:
 controlling, by the power controller, the power states of the system interconnect, the first core, and the second core in accordance with a specified power limit. 
 
     
     
         17 . The method of  claim 14  wherein controlling further comprises:
 attempting to optimize performance within a specified thermal budget. 
 
     
     
         18 . The method of  claim 15  wherein the first core is to operate at a first frequency in a first power state, the second core is to operate at a second frequency in a second power state, and the system interconnect is to operate at a third frequency in a third power state. 
     
     
         19 . The method of  claim 17  further comprising:
 providing a portion of the first thermal data from a third thermal sensor associated with the first core. 
 
     
     
         20 . The method of  claim 14  wherein a functional unit is coupled to the plurality of cores over the system interconnect and a cache is shared by the plurality of cores. 
     
     
         21 . The method of  claim 20 , wherein a memory controller is coupled to the system interconnect and a system memory device. 
     
     
         22 . The method of  claim 21 , wherein a network interface is coupled to the system interconnect, a flash memory is coupled to the interconnect, and a display is coupled to the system interconnect. 
     
     
         23 . The method of  claim 14 , wherein controlling further comprises the power controller determining whether to modify a power state of one of the plurality of cores based on the first thermal data and/or the second thermal data. 
     
     
         24 . The method of  claim 23  wherein controlling further comprises the power controller determining whether to modify a power state of one of the plurality of cores based on current power states of the plurality of cores and the power limit. 
     
     
         25 . The method of  claim 14  wherein controlling further comprises the power controller determining whether to modify a power state of one of the plurality of cores based on performance data determined from one or more of the plurality of counters. 
     
     
         26 . The method of  claim 14  wherein the plurality of counters comprise a first plurality of counters, the method further comprising:
 counting, by a second plurality of counters integral to the second core, a corresponding number of occurrences of architectural events, the plurality of counters including a first counter to count a number of instructions retired, a second counter to count last level cache misses, a third counter to count translation lookaside buffer (TLB) misses, and a fourth counter to count branch mispredictions. 
 
     
     
         27 . A system comprising:
 a system memory to store program code and data; and   a processor coupled to the memory, the processor comprising:
 a plurality of cores including a first core of a first core type and a second core of a second core type, wherein the first core and second core are able to operate concurrently at different frequencies in different power states; 
 a plurality of thermal sensors to provide thermal data, including at least a first thermal sensor to provide first thermal data for the first core and at least a second thermal sensor to provide second thermal data for the second core; 
 a plurality of counters integral to the first core, each counter to count a number of occurrences of one of the architectural events, the plurality of counters including a first counter to count a number of instructions retired, a second counter to count last level cache misses, a third counter to count translation lookaside buffer (TLB) misses, and a fourth counter to count branch mispredictions; 
 a system interconnect coupled to the plurality of cores, the system interconnect able to operate in a plurality of different power states; and 
 a power controller coupled to the system interconnect, the power controller to control the power states of the first core and the second core in accordance with the thermal data. 
   
     
     
         28 . The system of  claim 27  wherein the power controller to control the power states of the interconnect in accordance with the thermal data. 
     
     
         29 . The system of  claim 28  wherein the power controller is to control the power states of the system interconnect, the first core, and the second core in accordance with a specified power limit. 
     
     
         30 . The system of  claim 27  wherein the power controller is to attempt to optimize performance within a specified thermal budget. 
     
     
         31 . The system of  claim 28  wherein the first core is to operate at a first frequency in a first power state, the second core is to operate at a second frequency in a second power state, and the system interconnect is to operate at a third frequency in a third power state. 
     
     
         32 . The system of  claim 30  further comprising:
 a third thermal sensor in combination with the first thermal sensor to provide the first thermal data for the first core. 
 
     
     
         33 . The system of  claim 27  further comprising:
 a functional unit coupled to the plurality of cores over the system interconnect; and 
 a cache shared by the plurality of cores. 
 
     
     
         34 . The system of  claim 33 , further comprising:
 a memory controller coupled to the system interconnect and the system memory.   
     
     
         35 . The system of  claim 34 , further comprising:
 a network interface coupled to the system interconnect;   a flash memory coupled to the interconnect; and   a display coupled to the system interconnect.   
     
     
         36 . The system of  claim 27 , wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on the first thermal data and/or the second thermal data. 
     
     
         37 . The system of  claim 27  wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on current power states of the plurality of cores and the power limit. 
     
     
         38 . The system of  claim 27  wherein the power controller is to determine whether to modify a power state of one of the plurality of cores based on performance data determined from one or more of the plurality of counters. 
     
     
         39 . The system of  claim 27  wherein the plurality of counters integral to the first core comprise a first plurality of counters, the system further comprising: a second plurality of counters integral to the second core, each counter of the second plurality of counters to count a number of occurrences of one of the architectural events, the second plurality of counters including a fifth counter to count a number of instructions retired, a sixth counter to count last level cache misses, a seventh counter to count translation lookaside buffer (TLB) misses, and an eighth counter to count branch mispredictions.