Integrated circuits having in-situ constraints

Abstract

In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Enhanced physical design tools are provided to read and process anisotropic design rules.

What is claimed is: 
     
         1 . An integrated circuit manufactured using an integrated circuit fabrication system in a process comprising:
 detecting at least one area in a design layout according to a plurality of original design rules and an optimization that includes a layout object-specific layout pattern, wherein the original design rules comprise limits on minimum distance between layout objects represented in the layout object-specific layout pattern;   modifying the design layout by including a layout object-specific layout pattern modification to the plurality of original design rules which comprise limits on the minimum distance between the layout objects, which increases the minimum distance between the layout objects above at least one respective original design rule on the minimum distance between the layout objects associated with the at least one area, while enforcing the plurality of original design rules which comprise limits on the minimum distance between the layout objects, to generate a modified design layout; and   providing the modified design layout as an output.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the layout object-specific layout pattern modification is determined based on a look-up data table, such that each occurrence of the layout object-specific layout pattern is associated with a respective layout object-specific layout pattern modification to the plurality of original design rules. 
     
     
         3 . The integrated circuit of  claim 1 , wherein a layout object-specific layout pattern in the at least one area is employed as a pattern key to search a look-up table, such that each occurrence of the layout object-specific layout pattern is associated with a respective layout object-specific layout pattern modification to the plurality of original design rules. 
     
     
         4 . The integrated circuit of  claim 3 , wherein a pattern of two adjacent layout objects in the at least one area is employed as a geometry combination pattern key to search a look-up table, such that each occurrence of the pattern of two adjacent layout objects is associated with a respective layout object-specific layout pattern modification to the plurality of original design rules. 
     
     
         5 . The integrated circuit of  claim 1 , wherein the layout objects comprise adjacent spaced lines. 
     
     
         6 . A method of producing a photolithography design, comprising:
 providing a netlist, a set of global design rules comprising at least global rules limiting relative distances of layout objects of a photolithography design layout and an original design layout of layout objects dependent on the set of global design rules, that has poor process latitude;   automatically recognizing patterns of interacting layout objects within the original design layout that cause the poor process latitude;   automatically modifying the set of global design rules according to pattern-specific design rules which remedy poor process latitude by the recognized patterns of interacting layout objects within the original design layout, to produce a modified set of design rules; and   automatically modifying the original design layout according to the modified set of design rules to produce a modified design layout, wherein the modified design layout meets the netlist and the set of global design rules, and differs from the original design layout.   
     
     
         7 . The method according to  claim 6 , further comprising outputting the modified design layout. 
     
     
         8 . The method according to  claim 7 , further comprising manufacturing an integrated circuit based on the output modified design layout. 
     
     
         9 . A method of producing a photolithographic design defining a plurality of layout objects in a photolithographic process, comprising:
 automatically laying out the plurality of layout objects in an initial photolithography design layout according to general design rules comprising at least one minimum distance rule and a design layout optimization;   automatically detecting at least one critical area of the initial photolithography design layout based on an adverse effect of process latitude on the photolithographic process with respect to the at least one critical area;   automatically selectively modifying the initial photolithography design layout, to define a modified photolithography design layout, the modified photolithography design layout having a local alteration of the at least one minimum distance rule dependent on a pattern of layout objects in a specific location of the original design layout to at least partially remedy the adverse effect of the process latitude on the photolithographic process with respect to the at least one critical area; and   outputting the modified photolithography design layout.   
     
     
         10 . The method according to  claim 9 , wherein the at least one minimum distance rule applied to the at least one critical area produces the initial photolithography design layout predicted to have a first photolithographic manufacturing yield, and the modified photolithography design layout, predicted to have a second manufacturing yield, wherein the second manufacturing yield is greater than the first manufacturing yield. 
     
     
         11 . The method according to  claim 9 , further comprising manufacturing at least one of a photolithographic product and a photolithographic mask corresponding to the modified photolithographic design layout. 
     
     
         12 . The method according to  claim 9 , wherein the design payout optimization, optimizes according to an objective function. 
     
     
         13 . The method according to  claim 9 , wherein at least a portion of the at least one minimum distance rule comprises anisotropic minimum distance rules. 
     
     
         14 . The method according to  claim 9 , wherein the initial photolithography design layout comprises a first plurality of routing wires running in a first direction, and a second plurality of routing wires running in a second direction, the second direction being orthogonal to the first direction, the routing wires of the first plurality of routing wires having first width values, the routing wires of the second plurality of routing wires having second width values, the first width values being substantially different from the second width values. 
     
     
         15 . The method according to  claim 14 , wherein the step of automatically selectively modifying the initial photolithography design layout comprises at least one of
 (a) locally adjusting at least a width value of at least one of the first plurality of routing wires; and   (b) locally adjusting at least a spacing value between a pair of the first plurality of routing wires.   
     
     
         16 . The method according to  claim 9 , wherein the initial photolithography design layout comprises interrelated layout objects organized in a hierarchical structure including master instances, cell instances, and array instances. 
     
     
         17 . The method according to  claim 9 , wherein the pattern of layout objects within the initial photolithography design layout comprises interrelated layout objects on one layer of the initial photolithography design layout. 
     
     
         18 . The method according to  claim 9 , wherein the pattern of layout objects is determined by performing automated pattern recognition of combinations of geometry in the initial photolithography design layout. 
     
     
         19 . The method according to  claim 9 , wherein:
 the general design rules comprise a minimum safeguard distance limit; and   the step of automatically selectively modifying the initial photolithography design layout comprises generating an additional safeguard distance, and adding the additional safeguard distance to the minimum safeguard distance limit.   
     
     
         20 . The method according to  claim 9 , further comprising further modifying the modified photolithography design layout selectively dependent on a circuit tolerance of structures defined by the pattern of layout objects in the specific location. 
     
     
         21 . The method according to  claim 9 , wherein said step of automatically selectively modifying the initial photolithography design layout comprises modifying the general design layout by optimizing according to an optimization objective in a presence of constraints imposed by at least the pattern of layout objects. 
     
     
         22 . The method according to  claim 9 , wherein said step of generating the modified design layout causes at least one new violation of the original design rules comprising at least one minimum distance rule, further comprising optimizing the modified photolithography design layout according to at least one optimization objective.