Semiconductor memory device

Abstract

A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a semiconductor substrate;   a first wiring layer above the semiconductor substrate;   a second wiring layer above the first wiring layer;   a memory pillar extending in a first direction intersecting the semiconductor substrate through the first and second wiring layers, the memory pillar comprising a charge storage layer;   a first plug contacting and electrically connected to the first wiring layer;   a first insulating layer above the first wiring layer; and   a first pillar located next to the first plug and extending through the first wiring layer and the first insulating layer and not through the second wiring layer, wherein   the first pillar includes a first semiconductor layer and a first pillar body provided on the first semiconductor layer,   the first pillar body extends through the first insulating layer in the first direction, and   the first pillar body includes a conductive layer extending in the first direction and an insulating layer containing a first region between the conductive layer and the first semiconductor layer and a second region between the conductive layer and the first insulating layer.   
     
     
         2 . The semiconductor memory device according to  claim 1 , wherein
 the first region is a bottom region below the conductive layer and above the conductive layer, and   the second region is a side region around a side surface of the conductive layer.   
     
     
         3 . The semiconductor memory device according to  claim 1 , wherein
 the first insulating layer is located on the semiconductor substrate,   the memory pillar is electrically connected to the semiconductor substrate, and   the first pillar contacts the semiconductor substrate.   
     
     
         4 . The semiconductor memory device according to  claim 1 , wherein the first pillar includes a second insulating layer, a charge storage layer, and a third insulating layer that are provided on a side surface of the conductive layer. 
     
     
         5 . The semiconductor memory device according to  claim 1 , wherein
 the first wiring layer includes a first terrace at which the first plug is connected to the first wiring layer.   
     
     
         6 . The semiconductor memory device according to  claim 1 , further comprising:
 a bit line connected to the memory pillar;   a sense amplifier connected to the memory pillar through the bit line; and   a row decoder connected to the first plug.   
     
     
         7 . The semiconductor memory device according to  claim 1 , wherein a distance between an upper surface of the first semiconductor layer and the semiconductor substrate is greater than a distance between an upper surface of the first wiring layer and the semiconductor substrate, and less than a distance between a bottom surface of the second wiring layer and the semiconductor substrate. 
     
     
         8 . The semiconductor memory device according to  claim 1 , further comprising:
 a plurality of word lines spaced from one another in the first direction and extending in a second direction crossing the first direction, wherein adjacent ones of the word lines in the first direction are connected to contacts adjacent to one another in the second direction.   
     
     
         9 . The semiconductor memory device according to  claim 1 , further comprising:
 a plurality of word lines spaced from one another in the first direction and extending in a second direction crossing the first direction, wherein adjacent ones of the word lines in the first direction are connected to contacts adjacent to one another in one of the second direction and a third direction crossing the first and the second directions.   
     
     
         10 . The semiconductor memory device according to  claim 9 , further comprising:
 a source line extending between adjacent ones of the word lines in the third direction.