Enhanced security computer processor with mentor circuits

Abstract

A computing device includes a plurality of bins distributed in a plurality of frames, and a plurality of mentor circuits. The bins store information for variables. Each mentor circuit may be assigned to a particular one or more of the variables. The mentor circuits perform cache management and operand addressing operations with respect to the particular variables to which the mentor circuit is assigned. A control circuit controls a main program flow.

1 - 56 . (canceled) 
     
     
         57 . A computing device, comprising:
 a main memory;   a local high speed memory configured to implement a frames/bins structure, wherein the local high speed memory comprises:   a plurality of frames, each of at least two of the frames comprising a physical memory element;   a plurality of bins distributed in the plurality of frames, wherein each of at least two of the bins comprises a logical element;   one or more functional units configured to perform operations relating to one or more variables stored in at least one of the bins, wherein each of at least one of the Variables comprises one or more words;   one or more interconnects between the main memory and the local high speed memory; and   one or more interconnects between the local high speed memory and the one or more functional units.   
     
     
         58 - 60 . (canceled) 
     
     
         61 . The computing device of  claim 57 , wherein each of at least one of the bins is distributed across two or more of the frames. 
     
     
         62 . The computing device of  claim 57 , further comprising one or more mentor circuits configured to control operations using at least one Variable stored in at least one of the bins. 
     
     
         63 - 69 . (canceled) 
     
     
         70 . The computing device of  claim 57 , further comprising one or more tarmac registers, wherein the tarmac registers are configured for staging of at least one operation. 
     
     
         71 . The computing device of  claim 57 , wherein the processor is configured to perform speculative execution on at least one Variable. 
     
     
         72 - 78 . (canceled) 
     
     
         79 . The computing device of  claim 57 , wherein at least one of the variables corresponds to a physical device used or controlled by the computing device. 
     
     
         80 . The computing device of  claim 57 , wherein at least one of the Variables corresponds to instrumentation or a sensor used or controlled by the computing device. 
     
     
         81 - 82 . (canceled) 
     
     
         83 . A method of computing, comprising:
 providing a plurality of frames in a high speed local memory, wherein the local high speed memory is coupled to a main memory by one or more interconnects and to one or more functional units by one or more interconnects, wherein each of at least two of the frames comprises a physical memory element; and   storing a plurality of variables in one or more bins distributed in the plurality of frames, wherein each of at least two of the bins comprises a logical element; and   performing, by a processor, one or more operations relating to at least one of the one or more variables stored in at least one of the bins, wherein each of at least one of the variables comprises two or more words.   
     
     
         84 - 88 . (canceled) 
     
     
         89 . The method of  claim 83 , wherein each of at least one of the bins is distributed across two or more of the frames. 
     
     
         90 . The method of  claim 83 , further comprising controlling, by one or more mentor circuits, operations using at least one Variable stored in at least one of the bins. 
     
     
         91 - 92 . (canceled) 
     
     
         93 . The method of  claim 83 , wherein at least one of the mentor circuits is configured to implement a self-bounds check for at least one of Variables. 
     
     
         94 . The method of  claim 83 , wherein at least one of the mentor circuits is configured to implement an intrusion bounds check for at least one of Variables. 
     
     
         95 . The method of  claim 83 , wherein one or more interconnects between the local high speed memory and the one or more functional units comprise:
 one or more frames/bins interconnect circuits going to the one or more functional units; and   one or more frames/bins interconnect circuits coming from the one or more functional units.   
     
     
         96 - 97 . (canceled) 
     
     
         98 . The method of  claim 83 , wherein performing at least one operation comprises staging at least one operation using a tarmac register. 
     
     
         99 . The method of  claim 83 , further comprising performing speculative execution on at least one variable. 
     
     
         100 - 104 . (canceled) 
     
     
         105 . The method of  claim 83 , wherein each of at least one of the variables comprises a set of operands. 
     
     
         106 . The method of  claim 83 , wherein each of at least one of the Variables corresponds to a conceptual unit. 
     
     
         107 . The method of  claim 83 , wherein at least one of the Variables corresponds to a physical device used or controlled by the computing device for interactions with instrumentation. 
     
     
         108 . The method of  claim 83 , wherein at least one of the Variables corresponds to a functional element of a system used or controlled by the computing device for providing communications links. 
     
     
         109 . A computing device, comprising:
 a main memory;   a local high speed memory comprising one or more bins, wherein each of at least two of the bins is configured to store a Variable;   one or more functional units configured to perform operations relating to one or more Variables stored in the local high speed memory;   one or more interconnects between the main memory and the local high speed memory;   one or more interconnects between the local high speed memory and the one or more functional units; and   one or more mentor circuits configured to control operations relating to at least one Variable stored in at least one of the bins.   
     
     
         110 - 186 . (canceled)