Method and system of verifying proper execution of a secure mode entry sequence

Abstract

A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.

What is claimed is: 
     
         1 . A method comprising:
 delivering, by an instructions bus, an instruction from a memory to a processor;   attempting to execute the instruction, by the processor; and   allowing, by a monitoring circuit, the processor to enter into a secure mode of operation, in response to confirming, by the monitoring circuit, proper execution of the instruction by the processor, wherein confirming the proper execution of the instruction by the processor comprises checking an interface bus of a trace port of the processor to determine that the processor identified the instruction as not a speculatively executed instruction.   
     
     
         2 . The method of  claim 1 , wherein confirming proper execution of the instruction by the processor further comprises checking the interface bus of the trace port of the processor to determine that an instruction set mode of the processor is the same as an instruction set type of the instruction. 
     
     
         3 . The method of  claim 1 , wherein confirming proper execution of the instruction by the processor further comprises checking the interface bus of the trace port of the processor to determine that the processor did not experience an internal exception while attempting to execute the instruction. 
     
     
         4 . The method of  claim 1 , wherein confirming proper execution of the instruction by the processor further comprises checking the interface bus of the trace port of the processor to determine that the processor did not experience an abort while attempting to execute the instruction. 
     
     
         5 . An apparatus comprising:
 a memory;   a processor coupled to the memory by an instruction bus, the processor having a trace port having an address bus and an interface bus, the processor configured to:
 receive an instruction from the memory over the instruction bus; and 
 attempt to execute the instruction; and 
   a monitoring circuit coupled to the processor by the address bus of the trace port, wherein the monitoring circuit is configured to allow the processor to enter into a secure mode of operation, in response to determining proper execution of the instruction by the processor, wherein determining proper execution of the instruction comprises determining, using the interface bus of the trace port, that the processor identified the instruction as not a speculatively executed instruction.   
     
     
         6 . The apparatus of  claim 5 , wherein the monitoring circuit is a hardware-based security state machine. 
     
     
         7 . The apparatus of  claim 5 , wherein the monitoring circuit determining proper execution of the instruction comprises determining, using the interface bus of the trace port, that the processor has not experienced an internal exception while the processor attempts to execute the instruction. 
     
     
         8 . The apparatus of  claim 5  wherein the monitoring circuit checks the interface bus of the trace port to determine whether the processor experienced an abort while attempting to execute the instruction. 
     
     
         9 . The apparatus of  claim 5 , wherein the processor, the memory, and the monitoring circuit are integrated on a single die. 
     
     
         10 . The apparatus of  claim 5 , wherein the monitoring circuit issues a security violation signal to a power reset control manager, in response to determining improper execution of the instruction. 
     
     
         11 . The apparatus of  claim 5 , wherein the monitoring circuit determining proper execution of the instruction by the processor further comprises determining that the instruction was executed by the processor. 
     
     
         12 . The apparatus of  claim 5 , wherein the monitoring circuit further issues a security violation signal, in response to determining that the instruction was not executed. 
     
     
         13 . The apparatus of  claim 5 , wherein the monitoring circuit determining proper execution of the instruction by the processor further comprises determining that the processor has not experienced an internal exception during execution of the instruction. 
     
     
         14 . The apparatus of  claim 5 , wherein the monitoring circuit further issues a security violation signal, in response to determining that the processor experienced an internal exception during execution of the instruction. 
     
     
         15 . The apparatus of  claim 5 , wherein the monitoring circuit determining proper execution of the instruction by the processor further comprises determining that the processor has not experienced an abort during execution of the instruction. 
     
     
         16 . A method comprising:
 delivering, by an instruction bus, an instruction from a memory to a processor;   attempting to execute the delivered instruction, by the processor; and   preventing, by a monitoring circuit, the processor from entering a secure mode of operation, in response to determining that the delivered instruction is a speculatively executed instruction, using a trace port of the processor.   
     
     
         17 . The method of  claim 16 , further comprising checking an address bus of the trace port of the processor. 
     
     
         18 . The method of  claim 16 , further comprising checking an interface bus of the trace port of the processor. 
     
     
         19 . The method of  claim 16 , further comprising checking an interface bus of the trace port to determine whether the processor experienced an internal exception during execution of the delivered instruction. 
     
     
         20 . The method of  claim 16 , further comprising checking an interface bus of the trace port to determine whether the processor experienced an abort while attempting to execute the delivered instruction.